On 19 April 2016 at 14:58, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Future Tegra chips contain multiple entirely separate GPIO controllers. It is plausible that boards using those chips will end up with non-DT-driven code that manipulates GPIOs, just like a few Tegra boards do today. In that case, we'll want to make sure that the mapping from the global integer GPIO numbering to GPIO controller occurs in a defined order, so that the right GPIO is chosen in each case. To guarantee that order, GPIO controllers must have specific DM "seq" values. This can be ensured via DT aliases.
This is a no-op for current chips since there's only one GPIO controller. However, it provides a good example for cargo-cult programming:-)
The aliases are added to the SoC DTSI files since there is no need for them to vary between boards, and doing so avoids having to duplicate the entry in each board's DT file. Any additional board-specific GPIO controllers can be referenced by additional aliases (starting at 1) in board DT files if needed.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/dts/tegra114.dtsi | 4 ++++ arch/arm/dts/tegra20.dtsi | 4 ++++ arch/arm/dts/tegra210.dtsi | 4 ++++ arch/arm/dts/tegra30.dtsi | 4 ++++ 4 files changed, 16 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org