This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/powerpc/cpu/mpc85xx/Kconfig | 4 - board/socrates/Kconfig | 9 - board/socrates/MAINTAINERS | 6 - board/socrates/Makefile | 15 -- board/socrates/ddr.c | 56 ----- board/socrates/law.c | 44 ---- board/socrates/nand.c | 163 -------------- board/socrates/sdram.c | 96 --------- board/socrates/socrates.c | 434 ------------------------------------- board/socrates/tlb.c | 105 --------- board/socrates/upm_table.h | 59 ------ configs/socrates_defconfig | 5 - include/configs/socrates.h | 446 --------------------------------------- 13 files changed, 1442 deletions(-) delete mode 100644 board/socrates/Kconfig delete mode 100644 board/socrates/MAINTAINERS delete mode 100644 board/socrates/Makefile delete mode 100644 board/socrates/ddr.c delete mode 100644 board/socrates/law.c delete mode 100644 board/socrates/nand.c delete mode 100644 board/socrates/sdram.c delete mode 100644 board/socrates/socrates.c delete mode 100644 board/socrates/tlb.c delete mode 100644 board/socrates/upm_table.h delete mode 100644 configs/socrates_defconfig delete mode 100644 include/configs/socrates.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 3e8d0b1..127bd6f 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -11,9 +11,6 @@ choice config TARGET_SBC8548 bool "Support sbc8548"
-config TARGET_SOCRATES - bool "Support socrates" - config TARGET_B4860QDS bool "Support B4860QDS" select SUPPORT_SPL @@ -190,7 +187,6 @@ source "board/freescale/t4rdb/Kconfig" source "board/gdsys/p1022/Kconfig" source "board/keymile/kmp204x/Kconfig" source "board/sbc8548/Kconfig" -source "board/socrates/Kconfig" source "board/stx/stxgp3/Kconfig" source "board/stx/stxssa/Kconfig" source "board/xes/xpedite520x/Kconfig" diff --git a/board/socrates/Kconfig b/board/socrates/Kconfig deleted file mode 100644 index ca945c2..0000000 --- a/board/socrates/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_SOCRATES - -config SYS_BOARD - default "socrates" - -config SYS_CONFIG_NAME - default "socrates" - -endif diff --git a/board/socrates/MAINTAINERS b/board/socrates/MAINTAINERS deleted file mode 100644 index 293b8e6..0000000 --- a/board/socrates/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SOCRATES BOARD -#M: - -S: Maintained -F: board/socrates/ -F: include/configs/socrates.h -F: configs/socrates_defconfig diff --git a/board/socrates/Makefile b/board/socrates/Makefile deleted file mode 100644 index 79bda71..0000000 --- a/board/socrates/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# -# (C) Copyright 2008 -# Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += socrates.o -obj-y += law.o -obj-y += tlb.o -obj-y += nand.o -obj-y += sdram.o -obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c deleted file mode 100644 index 6bad4da..0000000 --- a/board/socrates/ddr.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 7; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/socrates/law.c b/board/socrates/law.c deleted file mode 100644 index 449a030..0000000 --- a/board/socrates/law.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2008 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x2fff_ffff DDR 512M - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xc00f_ffff FPGA 1M - * 0xc800_0000 0xcbff_ffff LIME 64M - * 0xe000_0000 0xe00f_ffff CCSR 1M (mapped by CCSRBAR) - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xfc00_0000 0xffff_ffff FLASH 64M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), -#if defined(CONFIG_SYS_FPGA_BASE) - SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -#endif - SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/socrates/nand.c b/board/socrates/nand.c deleted file mode 100644 index 15e6ea6..0000000 --- a/board/socrates/nand.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * (C) Copyright 2008 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#if defined(CONFIG_SYS_NAND_BASE) -#include <nand.h> -#include <asm/errno.h> -#include <asm/io.h> - -static int state; -static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte); -static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len); -static u_char sc_nand_read_byte(struct mtd_info *mtd); -static u16 sc_nand_read_word(struct mtd_info *mtd); -static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len); -static int sc_nand_device_ready(struct mtd_info *mtdinfo); - -#define FPGA_NAND_CMD_MASK (0x7 << 28) -#define FPGA_NAND_CMD_COMMAND (0x0 << 28) -#define FPGA_NAND_CMD_ADDR (0x1 << 28) -#define FPGA_NAND_CMD_READ (0x2 << 28) -#define FPGA_NAND_CMD_WRITE (0x3 << 28) -#define FPGA_NAND_BUSY (0x1 << 15) -#define FPGA_NAND_ENABLE (0x1 << 31) -#define FPGA_NAND_DATA_SHIFT 16 - -/** - * sc_nand_write_byte - write one byte to the chip - * @mtd: MTD device structure - * @byte: pointer to data byte to write - */ -static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte) -{ - sc_nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte)); -} - -/** - * sc_nand_write_buf - write buffer to chip - * @mtd: MTD device structure - * @buf: data buffer - * @len: number of bytes to write - */ -static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - int i; - struct nand_chip *this = mtd->priv; - - for (i = 0; i < len; i++) { - out_be32(this->IO_ADDR_W, - state | (buf[i] << FPGA_NAND_DATA_SHIFT)); - } -} - - -/** - * sc_nand_read_byte - read one byte from the chip - * @mtd: MTD device structure - */ -static u_char sc_nand_read_byte(struct mtd_info *mtd) -{ - u8 byte; - sc_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte)); - return byte; -} - -/** - * sc_nand_read_word - read one word from the chip - * @mtd: MTD device structure - */ -static u16 sc_nand_read_word(struct mtd_info *mtd) -{ - u16 word; - sc_nand_read_buf(mtd, (uchar *)&word, sizeof(word)); - return word; -} - -/** - * sc_nand_read_buf - read chip data into buffer - * @mtd: MTD device structure - * @buf: buffer to store date - * @len: number of bytes to read - */ -static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) -{ - int i; - struct nand_chip *this = mtd->priv; - int val; - - val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ; - - out_be32(this->IO_ADDR_W, val); - for (i = 0; i < len; i++) { - buf[i] = (in_be32(this->IO_ADDR_R) >> FPGA_NAND_DATA_SHIFT) & 0xff; - } -} - -/** - * sc_nand_device_ready - Check the NAND device is ready for next command. - * @mtd: MTD device structure - */ -static int sc_nand_device_ready(struct mtd_info *mtdinfo) -{ - struct nand_chip *this = mtdinfo->priv; - - if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY) - return 0; /* busy */ - return 1; -} - -/** - * sc_nand_hwcontrol - NAND control functions wrapper. - * @mtd: MTD device structure - * @cmd: Command - */ -static void sc_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) -{ - if (ctrl & NAND_CTRL_CHANGE) { - state &= ~(FPGA_NAND_CMD_MASK | FPGA_NAND_ENABLE); - - switch (ctrl & (NAND_ALE | NAND_CLE)) { - case 0: - state |= FPGA_NAND_CMD_WRITE; - break; - - case NAND_ALE: - state |= FPGA_NAND_CMD_ADDR; - break; - - case NAND_CLE: - state |= FPGA_NAND_CMD_COMMAND; - break; - - default: - printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl); - } - - if (ctrl & NAND_NCE) - state |= FPGA_NAND_ENABLE; - } - - if (cmd != NAND_CMD_NONE) - sc_nand_write_byte(mtdinfo, cmd); -} - -int board_nand_init(struct nand_chip *nand) -{ - nand->cmd_ctrl = sc_nand_hwcontrol; - nand->ecc.mode = NAND_ECC_SOFT; - nand->dev_ready = sc_nand_device_ready; - nand->read_byte = sc_nand_read_byte; - nand->read_word = sc_nand_read_word; - nand->write_buf = sc_nand_write_buf; - nand->read_buf = sc_nand_read_buf; - - return 0; -} - -#endif diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c deleted file mode 100644 index aebd02f..0000000 --- a/board/socrates/sdram.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * (C) Copyright 2008 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <fsl_ddr_sdram.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <spd_sdram.h> - - -#if !defined(CONFIG_SPD_EEPROM) -/* - * Autodetect onboard DDR SDRAM on 85xx platforms - * - * NOTE: Some of the hardcoded values are hardware dependant, - * so this should be extended for other future boards - * using this routine! - */ -phys_size_t fixed_sdram(void) -{ - struct ccsr_ddr __iomem *ddr = - (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); - - /* - * Disable memory controller. - */ - ddr->cs0_config = 0; - ddr->sdram_cfg = 0; - - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2; - ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL; - - asm ("sync;isync;msync"); - udelay(1000); - - ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG; - asm ("sync; isync; msync"); - udelay(1000); - - if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) { - /* - * OK, size detected -> all done - */ - return CONFIG_SYS_SDRAM_SIZE<<20; - } - - return 0; /* nothing found ! */ -} -#endif - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf ("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf ("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf ("SDRAM test passed.\n"); - return 0; -} -#endif diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c deleted file mode 100644 index 953a43f..0000000 --- a/board/socrates/socrates.c +++ /dev/null @@ -1,434 +0,0 @@ -/* - * (C) Copyright 2008 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003, Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt smcnutt@artesyncp.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <ioports.h> -#include <flash.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/io.h> -#include <i2c.h> -#include <mb862xx.h> -#include <video_fb.h> -#include "upm_table.h" - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[]; /* FLASH chips info */ -extern GraphicDevice mb862xx; - -void local_bus_init (void); -ulong flash_get_size (ulong base, int banknum); - -int checkboard (void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - char buf[64]; - int f; - int i = getenv_f("serial#", buf, sizeof(buf)); -#ifdef CONFIG_PCI - char *src; -#endif - - puts("Board: Socrates"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - -#ifdef CONFIG_PCI - /* Check the PCI_clk sel bit */ - if (in_be32(&gur->porpllsr) & (1<<15)) { - src = "SYSCLK"; - f = CONFIG_SYS_CLK_FREQ; - } else { - src = "PCI_CLK"; - f = CONFIG_PCI_CLK_FREQ; - } - printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src); -#else - printf ("PCI1: disabled\n"); -#endif - - /* - * Initialize local bus. - */ - local_bus_init (); - return 0; -} - -int misc_init_r (void) -{ - /* - * Adjust flash start and offset to detected values - */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Check if boot FLASH isn't max size - */ - if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) { - set_lbc_or(0, gd->bd->bi_flashstart | - (CONFIG_SYS_OR0_PRELIM & 0x00007fff)); - set_lbc_br(0, gd->bd->bi_flashstart | - (CONFIG_SYS_BR0_PRELIM & 0x00007fff)); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1); - } - - /* - * Check if only one FLASH bank is available - */ - if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { - set_lbc_or(1, 0); - set_lbc_br(1, 0); - - /* - * Re-do flash protection upon new addresses - */ - flash_protect (FLAG_PROTECT_CLEAR, - gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Redundant environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - } - - return 0; -} - -/* - * Initialize Local Bus - */ -void local_bus_init (void) -{ - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); - sys_info_t sysinfo; - uint clkdiv; - uint lbc_mhz; - uint lcrr = CONFIG_SYS_LBC_LCRR; - - get_sys_info (&sysinfo); - clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv; - - /* Disable PLL bypass for Local Bus Clock >= 66 MHz */ - if (lbc_mhz >= 66) - lcrr &= ~LCRR_DBYP; /* DLL Enabled */ - else - lcrr |= LCRR_DBYP; /* DLL Bypass */ - - out_be32 (&lbc->lcrr, lcrr); - asm ("sync;isync;msync"); - - out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */ - out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */ - out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */ - out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */ - - /* Init UPMA for FPGA access */ - out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */ - upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int)); - - /* Init UPMB for Lime controller access */ - out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */ - upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int)); -} - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxads_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - {} -}; -#endif - - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc85xxads_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void pci_init_board (void) -{ -#ifdef CONFIG_PCI - pci_mpc85xx_init (&hose); -#endif /* CONFIG_PCI */ -} - -#ifdef CONFIG_BOARD_EARLY_INIT_R -int board_early_init_r (void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - /* set and reset the GPIO pin 2 which will reset the W83782G chip */ - out_8((unsigned char*)&gur->gpoutdr, 0x3F ); - out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */ - udelay(200); - out_8( (unsigned char*)&gur->gpoutdr, 0x1F ); - - return (0); -} -#endif /* CONFIG_BOARD_EARLY_INIT_R */ - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - u32 val[12]; - int rc, i = 0; - - ft_cpu_setup(blob, bd); - - /* Fixup NOR FLASH mapping */ - val[i++] = 0; /* chip select number */ - val[i++] = 0; /* always 0 */ - val[i++] = gd->bd->bi_flashstart; - val[i++] = gd->bd->bi_flashsize; - - if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) { - /* Fixup LIME mapping */ - val[i++] = 2; /* chip select number */ - val[i++] = 0; /* always 0 */ - val[i++] = CONFIG_SYS_LIME_BASE; - val[i++] = CONFIG_SYS_LIME_SIZE; - } - - /* Fixup FPGA mapping */ - val[i++] = 3; /* chip select number */ - val[i++] = 0; /* always 0 */ - val[i++] = CONFIG_SYS_FPGA_BASE; - val[i++] = CONFIG_SYS_FPGA_SIZE; - - rc = fdt_find_and_setprop(blob, "/localbus", "ranges", - val, i * sizeof(u32), 1); - if (rc) - printf("Unable to update localbus ranges, err=%s\n", - fdt_strerror(rc)); - - return 0; -} -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ - -#define DEFAULT_BRIGHTNESS 25 -#define BACKLIGHT_ENABLE (1 << 31) - -static const gdc_regs init_regs [] = -{ - {0x0100, 0x00010f00}, - {0x0020, 0x801901df}, - {0x0024, 0x00000000}, - {0x0028, 0x00000000}, - {0x002c, 0x00000000}, - {0x0110, 0x00000000}, - {0x0114, 0x00000000}, - {0x0118, 0x01df0320}, - {0x0004, 0x041f0000}, - {0x0008, 0x031f031f}, - {0x000c, 0x017f0349}, - {0x0010, 0x020c0000}, - {0x0014, 0x01df01e9}, - {0x0018, 0x00000000}, - {0x001c, 0x01e00320}, - {0x0100, 0x80010f00}, - {0x0, 0x0} -}; - -const gdc_regs *board_get_regs (void) -{ - return init_regs; -} - -int lime_probe(void) -{ - uint cfg_br2; - uint cfg_or2; - int type; - - cfg_br2 = get_lbc_br(2); - cfg_or2 = get_lbc_or(2); - - /* Configure GPCM for CS2 */ - set_lbc_br(2, 0); - set_lbc_or(2, 0xfc000410); - set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901); - - /* Get controller type */ - type = mb862xx_probe(CONFIG_SYS_LIME_BASE); - - /* Restore previous CS2 configuration */ - set_lbc_br(2, 0); - set_lbc_or(2, cfg_or2); - set_lbc_br(2, cfg_br2); - - return (type == MB862XX_TYPE_LIME) ? 1 : 0; -} - -/* Returns Lime base address */ -unsigned int board_video_init (void) -{ - if (!lime_probe()) - return 0; - - mb862xx.winSizeX = 800; - mb862xx.winSizeY = 480; - mb862xx.gdfIndex = GDF_15BIT_555RGB; - mb862xx.gdfBytesPP = 2; - - return CONFIG_SYS_LIME_BASE; -} - -#define W83782D_REG_CFG 0x40 -#define W83782D_REG_BANK_SEL 0x4e -#define W83782D_REG_ADCCLK 0x4b -#define W83782D_REG_BEEP_CTRL 0x4d -#define W83782D_REG_BEEP_CTRL2 0x57 -#define W83782D_REG_PWMOUT1 0x5b -#define W83782D_REG_VBAT 0x5d - -static int w83782d_hwmon_init(void) -{ - u8 buf; - - if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1)) - return -1; - - i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80); - i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0); - i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40); - - buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL); - i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL, - buf | 0x80); - i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0); - i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47); - i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01); - - buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG); - i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, - (buf & 0xf4) | 0x01); - return 0; -} - -static void board_backlight_brightness(int br) -{ - u32 reg; - u8 buf; - u8 old_buf; - - /* Select bank 0 */ - if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) - goto err; - else - buf = old_buf & 0xf8; - - if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1)) - goto err; - - if (br > 0) { - /* PWMOUT1 duty cycle ctrl */ - buf = 255 / (100 / br); - if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) - goto err; - - /* LEDs on */ - reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); - if (!(reg & BACKLIGHT_ENABLE)); - out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), - reg | BACKLIGHT_ENABLE); - } else { - buf = 0; - if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) - goto err; - - /* LEDs off */ - reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); - reg &= ~BACKLIGHT_ENABLE; - out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg); - } - /* Restore previous bank setting */ - if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) - goto err; - - return; -err: - printf("W83782G I2C access failed\n"); -} - -void board_backlight_switch (int flag) -{ - char * param; - int rc; - - if (w83782d_hwmon_init()) - printf ("hwmon IC init failed\n"); - - if (flag) { - param = getenv("brightness"); - rc = param ? simple_strtol(param, NULL, 10) : -1; - if (rc < 0) - rc = DEFAULT_BRIGHTNESS; - } else { - rc = 0; - } - board_backlight_brightness(rc); -} - -#if defined(CONFIG_CONSOLE_EXTRA_INFO) -/* - * Return text to be printed besides the logo. - */ -void video_get_info_str (int line_number, char *info) -{ - if (line_number == 1) { - strcpy (info, " Board: Socrates"); - } else { - info [0] = '\0'; - } -} -#endif diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c deleted file mode 100644 index f3b093a..0000000 --- a/board/socrates/tlb.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * (C) Copyright 2008 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - - /* - * TLB 1: 64M Non-cacheable, guarded - * 0xfc000000 64M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - -#if defined(CONFIG_SYS_FPGA_BASE) - /* - * TLB 4: 1M Non-cacheable, guarded - * 0xc0000000 1M FPGA and NAND - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_1M, 1), -#endif - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xc8000000 16M LIME GDC framebuffer - * 0xc9fc0000 256K LIME GDC MMIO - * (0xcbfc0000 256K LIME GDC MMIO) - * MMIO is relocatable and could be at 0xcbfc0000 - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_64M, 1), - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 7+8: 512M DDR, cache disabled (needed for memory test) - * 0x00000000 512M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_256M, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/socrates/upm_table.h b/board/socrates/upm_table.h deleted file mode 100644 index 600d5f0..0000000 --- a/board/socrates/upm_table.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2008 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * Copyright 2004, 2007 Freescale Semiconductor, Inc. - * (C) Copyright 2003 Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __UPM_TABLE_H -#define __UPM_TABLE_H - -/* UPM Table Configuration Code for FPGA access */ -static const unsigned int UPMTableA[] = -{ - 0x00fcec00, 0x00fcec00, 0x00fcec00, 0x00fcec00, /* Words 0 to 3 */ - 0x00fcec00, 0x00fcfc00, 0x00fcfc00, 0x00fcec05, /* Words 4 to 7 */ - 0x00fcec00, 0x00fcec00, 0x00fcec04, 0x00fcec04, /* Words 8 to 11 */ - 0x00fcec04, 0x00fcec04, 0x00fcec04, 0x00fcec04, /* Words 12 to 15 */ - 0x00fcec04, 0x00fcec04, 0x0fffec00, 0xffffec00, /* Words 16 to 19 */ - 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 20 to 23 */ - 0x00ffec00, 0x00ffec00, 0x00f3ec00, 0x0fffec00, /* Words 24 to 27 */ - 0x0ffffc04, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 28 to 31 */ - 0x00ffec00, 0x00ffec00, 0x00f3ec04, 0x00f3ec04, /* Words 32 to 35 */ - 0x00f3ec04, 0x00f3ec04, 0x00f3ec04, 0x00f3ec04, /* Words 36 to 39 */ - 0x00f3ec04, 0x00f3ec04, 0x0fffec00, 0xffffec00, /* Words 40 to 43 */ - 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 44 to 47 */ - 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec00, /* Words 48 to 51 */ - 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec00, /* Words 52 to 55 */ - 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 56 to 59 */ - 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01 /* Words 60 to 63 */ -}; - -/* LIME UPM B Table Configuration Code */ -static unsigned int UPMTableB[] = -{ - 0x0ffefc00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */ - 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc04, 0x0ffffc01, /* Words 4 to 7 */ - 0x0ffefc00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 8 to 11 */ - 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc04, 0x0ffcfc04, /* Words 12 to 15 */ - 0x0ffcfc04, 0x0ffcfc04, 0x0ffcfc04, 0x0ffcfc04, /* Words 16 to 19 */ - 0x0ffcfc04, 0x0ffcfc04, 0x0ffffc00, 0xfffffc01, /* Words 20 to 23 */ - 0x0cfffc00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */ - 0x00fffc00, 0x00fffc00, 0x00fffc04, 0x0ffffc01, /* Words 28 to 31 */ - 0x0cfffc00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 32 to 35 */ - 0x00fffc00, 0x00fffc00, 0x00fffc04, 0x00fffc04, /* Words 36 to 39 */ - 0x00fffc04, 0x00fffc04, 0x00fffc04, 0x00fffc04, /* Words 40 to 43 */ - 0x00fffc04, 0x00fffc04, 0x0ffffc00, 0xfffffc01, /* Words 44 to 47 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 /* Words 60 to 63 */ -}; -#endif diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig deleted file mode 100644 index 37af82e..0000000 --- a/configs/socrates_defconfig +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_SOCRATES=y -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set diff --git a/include/configs/socrates.h b/include/configs/socrates.h deleted file mode 100644 index 292b514..0000000 --- a/include/configs/socrates.h +++ /dev/null @@ -1,446 +0,0 @@ -/* - * (C) Copyright 2008 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * Wolfgang Denk wd@denx.de - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao X.Xiao@motorola.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Socrates - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* new uImage format support */ -#define CONFIG_FIT 1 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8544 1 -#define CONFIG_SOCRATES 1 - -#define CONFIG_SYS_TEXT_BASE 0xfff80000 - -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ - -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ -#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ - -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -/* - * Only possible on E500 Version 2 or newer cores. - */ -#define CONFIG_ENABLE_36BIT_PHYS 1 - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66666666 -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x00C00000 - -#define CONFIG_SYS_CCSRBAR 0xE0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR2 -#undef CONFIG_FSL_DDR_INTERACTIVE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_DDR_SPD - -#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ - -#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ - -/* Hardcoded values, to use instead of SPD */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x3935D322 -#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 -#define CONFIG_SYS_DDR_MODE 0x00480432 -#define CONFIG_SYS_DDR_INTERVAL 0x030C0100 -#define CONFIG_SYS_DDR_CONFIG_2 0x04400000 -#define CONFIG_SYS_DDR_CONFIG 0xC3008000 -#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 -#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ - -/* - * Flash on the LocalBus - */ -#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ - -#define CONFIG_SYS_FLASH0 0xFE000000 -#define CONFIG_SYS_FLASH1 0xFC000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } - -#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ - -#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */ -#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */ -#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */ -#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */ - -#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ - -/* FPGA and NAND */ -#define CONFIG_SYS_FPGA_BASE 0xc0000000 -#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ -#define CONFIG_SYS_HMI_BASE 0xc0010000 -#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ -#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ - -#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_CMD_NAND - -/* LIME GDC */ -#define CONFIG_SYS_LIME_BASE 0xc8000000 -#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ -#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ -#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */ - -#define CONFIG_VIDEO -#define CONFIG_VIDEO_MB862xx -#define CONFIG_VIDEO_MB862xx_ACCEL -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_CONSOLE_EXTRA_INFO -#define VIDEO_FB_16BPP_PIXEL_SWAP -#define VIDEO_FB_16BPP_WORD_SWAP -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_SPLASH_SCREEN -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ - -/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */ -#define CONFIG_SYS_MB862xx_CCF 0x10000 -/* SDRAM parameter */ -#define CONFIG_SYS_MB862xx_MMR 0x4157BA63 - -/* Serial Port */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 102124 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 102124 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -/* I2C RTC */ -#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */ - -/* I2C W83782G HW-Monitoring IC */ -#define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */ - -/* I2C temp sensor */ -/* Socrates uses Maxim's DS75, which is compatible with LM75 */ -#define CONFIG_DTT_LM75 1 -#define CONFIG_DTT_SENSORS {4} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 125 -#define CONFIG_SYS_DTT_LOW_TEMP -55 -#define CONFIG_SYS_DTT_HYSTERESIS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 - -/* - * General PCI - * Memory space is mapped 1-1. - */ -#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ - -/* PCI is clocked by the external source at 33 MHz */ -#define CONFIG_PCI_CLK_FREQ 33000000 -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ - -#if defined(CONFIG_PCI) -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC - -#define TSEC1_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 1 - -#define TSEC1_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC3_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0,1] */ -#define CONFIG_ETHPRIME "TSEC0" -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ - -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_TIMESTAMP /* Print image info with ts */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_BMP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DTT -#undef CONFIG_CMD_EEPROM -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_USB -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ -#endif - - -#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ - -#define CONFIG_BOOTDELAY 1 /* -1 disables auto-boot */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Welcome on the ABB Socrates Board;" \ - "echo" - -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consdev=ttyS0\0" \ - "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ - "bootfile=/home/tftp/syscon3/uImage\0" \ - "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \ - "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \ - "uboot_addr=FFFA0000\0" \ - "kernel_addr=FE000000\0" \ - "fdt_addr=FE1E0000\0" \ - "ramdisk_addr=FE200000\0" \ - "fdt_addr_r=B00000\0" \ - "kernel_addr_r=200000\0" \ - "ramdisk_addr_r=400000\0" \ - "rootpath=/opt/eldk/ppc_85xxDP\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath\0" \ - "addcons=setenv bootargs $bootargs " \ - "console=$consdev,$baudrate\0" \ - "addip=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ - ":$hostname:$netdev:off panic=1\0" \ - "boot_nor=run ramargs addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addcons;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "update_uboot=tftp 100000 ${uboot_file};" \ - "protect off fffa0000 ffffffff;" \ - "era fffa0000 ffffffff;" \ - "cp.b 100000 fffa0000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "update_kernel=tftp 100000 ${bootfile};" \ - "era fe000000 fe1dffff;" \ - "cp.b 100000 fe000000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "update_fdt=tftp 100000 ${fdt_file};" \ - "era fe1e0000 fe1fffff;" \ - "cp.b 100000 fe1e0000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "update_initrd=tftp 100000 ${initrd_file};" \ - "era fe200000 fe9fffff;" \ - "cp.b 100000 fe200000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "clean_data=era fea00000 fff5ffff\0" \ - "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ - "load_usb=usb start;" \ - "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ - "boot_usb=run load_usb usbargs addcons;" \ - "bootm ${kernel_addr_r} - ${fdt_addr};" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run boot_nor" - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -/* USB support */ -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_PCI_OHCI 1 -#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */ -#define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2) -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_USB_STORAGE 1 - -#endif /* __CONFIG_H */