From: Suresh Gupta suresh.gupta@freescale.com
USB3PHY Observing Intermittent Failure in Rx This patch is adding the erratum for LS1043 and LS2080 SoCs.
Signed-off-by: Sriram Dash sriram.dash@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 43 ++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 5 +++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 12 ++++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 7 ++++ 4 files changed, 67 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index c42d778..4e9c718 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -74,6 +74,47 @@ static void erratum_a008997(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ }
+static void erratum_a009007(void) +{ +/* TODO:implement the out_be16 instead of writew which is taking +little endian style */ +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A) + u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY1; + writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI); + usb_phy = (u32 __iomem *)USB_PHY2; + writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI); + usb_phy = (u32 __iomem *)USB_PHY3; + writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI); +#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) + u32 __iomem *dcsr = (u32 __iomem *)DCSR_BASE; + writew(USB_PHY_RX_EQ_VAL_1, + (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_2, + (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_3, + (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_4, + (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_1, + (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_2, + (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_3, + (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_4, + (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI); +#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ +} + bool soc_has_dp_ddr(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -249,6 +290,7 @@ void fsl_lsch3_early_init_f(void) erratum_a009008(); erratum_a009798(); erratum_a008997(); + erratum_a009007(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. @@ -522,6 +564,7 @@ void fsl_lsch2_early_init_f(void) erratum_a010539(); erratum_a009798(); erratum_a008997(); + erratum_a009007(); } #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index e66253f..7d263fa 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -114,6 +114,11 @@
#define CONFIG_SYS_FSL_ERRATUM_A008751 #define CONFIG_SYS_FSL_ERRATUM_A009798 +#define CONFIG_SYS_FSL_ERRATUM_A008997 +#define CONFIG_SYS_FSL_ERRATUM_A009007 +#define CONFIG_SYS_FSL_ERRATUM_A010165 + +
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 554def5..2634195 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -206,6 +206,18 @@ struct ccsr_gur { #define SCFG_USB3PRM2CR_USB3 0x08c #define USB_TXVREFTUNE 0x9 #define USB_SQRXTUNE 0xFC7FFFFF +#define USB_PCSTXSWINGFULL 0x47 +#define USB_PHY1 0x084F0000 +#define USB_PHY2 0x08500000 +#define USB_PHY3 0x08510000 +#define USB_PHY_RX_OVRD_IN_HI 0x200c +/* TODO : make it generic */ +#define USB_PHY_RX_EQ_VAL_1 0x0000 +#define USB_PHY_RX_EQ_VAL_2 0x8000 +#define USB_PHY_RX_EQ_VAL_3 0x8003 + +#define USB_PHY_RX_EQ_VAL_4 0x800b +
u32 devdisr2; /* Device disable control 2 */ u32 devdisr3; /* Device disable control 3 */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index b428b18..a7a9364 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -120,6 +120,13 @@ #define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
#define DCFG_DCSR_BASE 0X700100000ULL +#define DCSR_USB_PHY1 0x4600000 +#define DCSR_USB_PHY2 0x4610000 +#define DCSR_USB_PHY_RX_OVRD_IN_HI 0x1006 +#define USB_PHY_RX_EQ_VAL_1 0x0000 +#define USB_PHY_RX_EQ_VAL_2 0x0080 +#define USB_PHY_RX_EQ_VAL_3 0x0380 +#define USB_PHY_RX_EQ_VAL_4 0x0b80 #define DCFG_DCSR_PORCR1 0x000
/* Interrupt Sampling Control */