Hi Jagan,
-----Original Message----- From: Jagan Teki jagan@amarulasolutions.com Sent: Thursday, June 25, 2020 11:13 PM To: Sagar Kadam sagar.kadam@sifive.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen rick@andestech.com; Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt palmer@dabbelt.com; Anup Patel anup.patel@wdc.com; Atish Patra atish.patra@wdc.com; Lukasz Majewski lukma@denx.de; Pragnesh Patel pragnesh.patel@sifive.com; bin.meng@windriver.com; Simon Glass sjg@chromium.org; Trevor Woerner twoerner@gmail.com; Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com; Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals available in prci
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On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam sagar.kadam@sifive.com wrote:
Add bit indexes for reset signals within the PRCI module on FU540-C000 SoC. The DDR and ethernet sub-system's have reset signals indicated by these reset indexes.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com Reviewed-by: Pragnesh Patel Pragnesh.patel@sifive.com Reviewed-by: Bin Meng bin.meng@windriver.com
include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-
bindings/clock/sifive-fu540-prci.h
index 6a0b70a..1c03b09 100644 --- a/include/dt-bindings/clock/sifive-fu540-prci.h +++ b/include/dt-bindings/clock/sifive-fu540-prci.h @@ -15,4 +15,12 @@ #define PRCI_CLK_GEMGXLPLL 2 #define PRCI_CLK_TLCLK 3
+/* Reset bit indexes to be used by driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define PRCI_RST_RSVD_N 4 +#define PRCI_RST_GEMGXL_N 5 #endif
Do these bindings are synced from Linux? If Yes better to sync with a particular commit or tag rather than patch.
No, these reset bindings are not synced from Linux.
Thanks & Regards, Sagar
Jagan.