Do the reset before clearing the MSR, otherwise it may result in a read or write operation instead if the start condition is repeated.
Signed-off-by: Ismael Luceno ismael.luceno@silicon-gears.com Reviewed-by: Marek Vasut marek.vasut+renesas@gmail.com Reviewed-by: Heiko Schocher hs@denx.de ---
Notes: Changes since v1: - Rebased on top of patch 1050650 ("i2c: rcar_i2c: Add Gen3 SoC support")
drivers/i2c/rcar_i2c.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c index d7b27204cb..a88fbcf34f 100644 --- a/drivers/i2c/rcar_i2c.c +++ b/drivers/i2c/rcar_i2c.c @@ -134,9 +134,11 @@ static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read) }
writel((chip << 1) | read, priv->base + RCAR_I2C_ICMAR); - writel(0, priv->base + RCAR_I2C_ICMSR); + /* Reset */ writel(RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE | RCAR_I2C_ICMCR_ESG, priv->base + RCAR_I2C_ICMCR); + /* Clear Status */ + writel(0, priv->base + RCAR_I2C_ICMSR);
ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, mask, true, 100, true);