Re: [U-Boot] [PATCH] arm: rmobile: Add supoprt for KMC KZM-A9-GT board

Hi Nobuhiro,

On Thu, 21 Jun 2012 15:23:39 +0900, Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com wrote :

The KZM-A9-GT board has Renesas R-Mobile SH73A0, 512MB DDR2-SDRAM, USB, Ethernet, and more.

This patch supports the following functions:

• 512MB DDR2-SDRAM
• 16MB NOR Flash memory
• Serial console (SCIF)
• Ethernet (SMSC)
• I2C

Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com

arch/arm/include/asm/mach-types.h | 2 + board/kmc/kzm/Makefile | 51 ++++++ board/kmc/kzm/kzm.c | 142 +++++++++++++++++ board/kmc/kzm/lowlevel_init.S | 308 +++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/kzm_a9_gt.h | 164 ++++++++++++++++++++ 6 files changed, 668 insertions(+) create mode 100644 board/kmc/kzm/Makefile create mode 100644 board/kmc/kzm/kzm.c create mode 100644 board/kmc/kzm/lowlevel_init.S create mode 100644 include/configs/kzm_a9_gt.h

Board should be also added to MAINTAINERS

diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 2d5c3bc..98c992c 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1106,6 +1106,8 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_ATDGP318 3494 #define MACH_TYPE_OMAP5_SEVM 3777

+#define MACH_TYPE_KZM9G 4140

#ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type # undef machine_arch_type diff --git a/board/kmc/kzm/Makefile b/board/kmc/kzm/Makefile new file mode 100644 index 0000000..8601230 --- /dev/null +++ b/board/kmc/kzm/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2012 Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com +# (C) Copyright 2012 Renesas Solutions Corp. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +#

+include $(TOPDIR)/config.mk

+LIB = $(obj)lib$(BOARD).o

+COBJS := kzm.o +SOBJS := lowlevel_init.o

+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS))

+$(LIB): $(obj).depend $(OBJS) $(SOBJS)

• $(call cmd_link_o_target, $(OBJS) $(SOBJS))

+clean:

• rm -f $(SOBJS) $(OBJS)

+distclean: clean

• rm -f $(LIB) core *.bak $(obj) .depend

+#########################################################################

+# defines $(obj).depend target +include $(SRCTREE)/rules.mk

+sinclude $(obj).depend

+######################################################################### diff --git a/board/kmc/kzm/kzm.c b/board/kmc/kzm/kzm.c new file mode 100644 index 0000000..ae0868e --- /dev/null +++ b/board/kmc/kzm/kzm.c @@ -0,0 +1,142 @@ +/*

• • (C) Copyright 2012 Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com
• • (C) Copyright 2012 Renesas Solutions Corp.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <common.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <netdev.h> +#include <i2c.h>

+DECLARE_GLOBAL_DATA_PTR;

+#define CS0BCR_D (0x06C00400) +#define CS4BCR_D (0x06C00400) +#define CS0WCR_D (0x55062C42) +#define CS4WCR_D (0x19051443) +#define CMNCR_BROMMD0 (1 << 21) +#define CMNCR_BROMMD1 (1 << 22) +#define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1) +#define VCLKCR1_D (0x27)

+#define SMSTPCR1_CMT0 (1 << 24) +#define SMSTPCR1_I2C0 (1 << 16) +#define SMSTPCR3_USB (1 << 22)

+#define PORT32CR (0xE6051020) +#define PORT33CR (0xE6051021) +#define PORT34CR (0xE6051022) +#define PORT35CR (0xE6051023)

+int board_early_init_f(void) +{

• writel(CS0BCR_D, CS0BCR);
• writel(CS4BCR_D, CS4BCR);
• writel(CS0WCR_D, CS0WCR);
• writel(CS4WCR_D, CS4WCR);
• clrsetbits_le32(CMNCR, ~CMNCR_BROMMD, CMNCR_BROMMD);
• clrbits_le32(SMSTPCR1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
• clrbits_le32(SRCR1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
• clrbits_le32(SMSTPCR3, SMSTPCR3_USB);
• clrbits_le32(SRCR3, SMSTPCR3_USB);
• writel(VCLKCR1_D, VCLKCR1);
• /* Setup SCIF4 / workaround */
• writeb(0x12, PORT32CR);
• writeb(0x22, PORT33CR);
• writeb(0x12, PORT34CR);
• writeb(0x22, PORT35CR);
• return 0;

+}

+int board_init(void) +{

• sh73a0_pinmux_init();
• /* SCIFA 4 */
• gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
• gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
• gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
• gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
• /* Ethernet/SMSC */
• gpio_request(GPIO_PORT224, NULL);
• gpio_direction_input(GPIO_PORT224);
• /* SMSC/USB */
• gpio_request(GPIO_FN_CS4_, NULL);
• /* MMCIF */
• gpio_request(GPIO_FN_MMCCLK0, NULL);
• gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
• gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
• gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
• gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
• gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
• gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
• gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
• gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
• gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
• /* SDHI */
• gpio_request(GPIO_FN_SDHIWP0, NULL);
• gpio_request(GPIO_FN_SDHICD0, NULL);
• gpio_request(GPIO_FN_SDHICMD0, NULL);
• gpio_request(GPIO_FN_SDHICLK0, NULL);
• gpio_request(GPIO_FN_SDHID0_3, NULL);
• gpio_request(GPIO_FN_SDHID0_2, NULL);
• gpio_request(GPIO_FN_SDHID0_1, NULL);
• gpio_request(GPIO_FN_SDHID0_0, NULL);
• gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
• gpio_request(GPIO_PORT15, NULL);
• gpio_direction_output(GPIO_PORT15, 1);
• /* I2C */
• gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
• gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
• gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
• return 0;

+}

+int dram_init(void) +{

• gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
• return 0;

+}

+int board_eth_init(bd_t *bis) +{

• int ret = 0;

+#ifdef CONFIG_SMC911X

• ret = smc911x_initialize(0, CONFIG_SMC911X_BASE);

+#endif

• return ret;

+}

+void reset_cpu(ulong addr) +{ +} diff --git a/board/kmc/kzm/lowlevel_init.S b/board/kmc/kzm/lowlevel_init.S new file mode 100644 index 0000000..5221611 --- /dev/null +++ b/board/kmc/kzm/lowlevel_init.S @@ -0,0 +1,308 @@ +/*

• • Copyright (C) 2012 Nobuhiro Iwamatsu nobuhiro.Iwamatsu.yj@renesas.com
• • Copyright (C) 2012 Renesas Solutions Corp.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <config.h> +#include <asm/macro.h>

+/* loop until a value was compare */ +.macro cmp_loop, addr, data, cmp

• ldr r0, =\addr
• ldr r1, =\data
• ldr r2, =\cmp

+2:

• ldr r3, [r0, #0]
• and r3, r1, r3
• cmp r2, r3
• bne 2b

+.endm

+/* read value from addr, and calc OR with data */ +.macro or_write32, addr, data

• ldr r4, =\addr
• ldr r5, =\data
• ldr r6, [r4]
• orr r5, r6, r5
• str r5, [r4]

+.endm

+/* read value from addr, and calc AND with data */ +.macro and_write32, addr, data

• ldr r4, =\addr
• ldr r5, =\data
• ldr r6, [r4]
• and r5, r6, r5
• str r5, [r4]

+.endm

+.globl lowlevel_init

+lowlevel_init:

• ldr r0, =MERAM_BASE
• mov r1, #0x0
• str r1, [r0]
• mrc p15, 0, r0, c0, c0, 5
• ands r0, r0, #0xF
• beq lowlevel_init__
• b wait_interrupt
• .pool
• .align 4

+wait_interrupt:

• ldr r1, =ICCICR
• mov r2, #0x0
• str r2, [r1]
• mov r2, #0xF0
• ldr r1, =ICCPMR
• str r2, [r1]
• ldr r1, =ICCICR
• mov r2, #0x1
• str r2, [r1]

+wait_loop:

• wfi
• ldr r2, [r1, #0xC]
• str r2, [r1, #0x10]
• ldr r0, =MERAM_BASE
• ldr r2, [r0]
• cmp r2, #0
• movne pc, r2
• b wait_loop

+wait_loop_end:

• .pool
• .align 4

+lowlevel_init__:

• mov r0, #0x200000

+loop0:

• subs r0, r0, #1
• bne loop0
• write16 RWTCSRA0, 0xA507
• .pool
• and_write32 LIFEC_SEC_SRC, 0xFFFFFFE7
• and_write32 SRCR3, 0xFFFF7FFF
• and_write32 SMSTPCR2,0xFFFBFFFF
• and_write32 SRCR2, 0xFFFBFFFF
• write32 PLLECR, 0x00000000
• cmp_loop PLLECR, 0x00000F00, 0x00000000
• cmp_loop FRQCRB, 0x80000000, 0x00000000
• write32 PLL0CR, 0x2D000000
• write32 PLL1CR, 0x17100000
• write32 FRQCRB, 0x96235880
• cmp_loop FRQCRB, 0x80000000, 0x00000000
• write32 FLCKCR, 0x0000000B
• and_write32 SMSTPCR0, 0xFFFFFFFD
• and_write32 SRCR0, 0xFFFFFFFD
• write32 SMGPIOTIME, 0x00000514
• write32 SMCMT2TIME, 0x00000514
• write32 SMCPGTIME, 0x00000514
• write32 SMSYSCTIME, 0x00000514
• write32 DVFSCR4, 0x00092000
• write32 DVFSCR5, 0x000000DC
• write32 PLLECR, 0x00000000
• cmp_loop PLLECR, 0x00000F00, 0x00000000
• write32 FRQCRA, 0x0012453C
• write32 FRQCRB, 0x80331350
• cmp_loop FRQCRB, 0x80000000, 0x00000000
• write32 FRQCRD, 0x00000B0B
• cmp_loop FRQCRD, 0x80000000, 0x00000000
• write32 PCLKCR, 0x00000003
• write32 VCLKCR1, 0x0000012F
• write32 VCLKCR2, 0x00000119
• write32 VCLKCR3, 0x00000119
• write32 ZBCKCR, 0x00000002
• write32 FLCKCR, 0x00000005
• write32 SD0CKCR, 0x00000080
• write32 SD1CKCR, 0x00000080
• write32 SD2CKCR, 0x00000080
• write32 FSIACKCR, 0x0000003F
• write32 FSIBCKCR, 0x0000003F
• write32 SUBCKCR, 0x00000080
• write32 SPUACKCR, 0x0000000B
• write32 SPUVCKCR, 0x0000000B
• write32 MSUCKCR, 0x0000013F
• write32 HSICKCR, 0x00000080
• write32 MFCK1CR, 0x0000003F
• write32 MFCK2CR, 0x0000003F
• write32 DSITCKCR, 0x00000107
• write32 DSI0PCKCR, 0x00000313
• write32 DSI1PCKCR, 0x0000130D
• write32 DSI0PHYCR, 0x2A800E0E
• write32 PLL0CR, 0x1E000000
• write32 PLL0CR, 0x2D000000
• write32 PLL1CR, 0x17100000
• write32 PLL2CR, 0x27000080
• write32 PLL3CR, 0x1D000000
• write32 PLL0STPCR, 0x00080000
• write32 PLL1STPCR, 0x000120C0
• write32 PLL2STPCR, 0x00012000
• write32 PLL3STPCR, 0x00000030
• write32 PLLECR, 0x0000000B
• cmp_loop PLLECR, 0x00000B00, 0x00000B00
• write32 DVFSCR3, 0x000120F0
• write32 MPMODE, 0x00000020
• write32 VREFCR, 0x0000028A
• write32 RMSTPCR0, 0xE4628087
• write32 RMSTPCR1, 0xFFFFFFFF
• write32 RMSTPCR2, 0x53FFFFFF
• write32 RMSTPCR3, 0xFFFFFFFF
• write32 RMSTPCR4, 0x00800D3D
• write32 RMSTPCR5, 0xFFFFF3FF
• write32 SMSTPCR2, 0x00000000
• write32 SRCR2, 0x00040000
• and_write32 PLLECR, 0xFFFFFFF7
• cmp_loop PLLECR, 0x00000800, 0x00000000
• write32 HPBCTRL6, 0x00000001
• cmp_loop HPBCTRL6, 0x00000001, 0x00000001
• write32 FRQCRD, 0x00001414
• cmp_loop FRQCRD, 0x80000000, 0x00000000
• write32 PLL3CR, 0x1D000000
• or_write32 PLLECR, 0x00000008
• cmp_loop PLLECR, 0x00000800, 0x00000800
• or_write32 DLLCNT0A, 0x00000002
• write32 SDGENCNTA, 0x00000005
• cmp_loop SDGENCNTA, 0xFFFFFFFF, 0x00000000
• write32 SDCR0A, 0xACC90159
• write32 SDCR1A, 0x00010059
• write32 SDWCRC0A, 0x50874114
• write32 SDWCRC1A, 0x33199B37
• write32 SDWCRC2A, 0x008F2313
• write32 SDWCR00A, 0x31020707
• write32 SDWCR01A, 0x0017040A
• write32 SDWCR10A, 0x31020707
• write32 SDWCR11A, 0x0017040A
• write32 SDDRVCR0A, 0x05555555
• write32 SDWCR2A, 0x30000000
• or_write32 SDPCRA, 0x00000080
• cmp_loop SDPCRA, 0x00000080, 0x00000080
• write32 SDGENCNTA, 0x00002710
• cmp_loop SDGENCNTA, 0xFFFFFFFF, 0x00000000
• write32 SDMRACR0A, 0x0000003F
• write32 SDMRA1, 0x00000000
• write32 SDGENCNTA, 0x000001F4
• cmp_loop SDGENCNTA, 0xFFFFFFFF, 0x00000000
• write32 SDMRACR0A, 0x0000FF0A
• write32 SDMRA3, 0x00000000
• write32 SDGENCNTA, 0x00000032
• cmp_loop SDGENCNTA, 0xFFFFFFFF, 0x00000000
• write32 SDMRACR0A, 0x00002201
• write32 SDMRA1, 0x00000000
• write32 SDMRACR0A, 0x00000402
• write32 SDMRA1, 0x00000000
• write32 SDMRACR0A, 0x00000403
• write32 SDMRA1, 0x00000000
• write32 SDMRA2, 0x00000000
• write32 SDMRTMPCRA, 0x88800004
• write32 SDMRTMPMSKA,0x00000004
• write32 RTCORA, 0xA55A0032
• write32 RTCORHA, 0xA55A000C
• write32 RTCSRA, 0xA55A2048
• or_write32 SDCR0A, 0x00000800
• or_write32 SDCR1A, 0x00000400
• write32 ZQCCRA, 0xFFF20000
• or_write32 DLLCNT0B, 0x00000002
• write32 SDGENCNTB, 0x00000005
• cmp_loop SDGENCNTB, 0xFFFFFFFF, 0x00000000
• write32 SDCR0B, 0xACC90159
• write32 SDCR1B, 0x00010059
• write32 SDWCRC0B, 0x50874114
• write32 SDWCRC1B, 0x33199B37
• write32 SDWCRC2B, 0x008F2313
• write32 SDWCR00B, 0x31020707
• write32 SDWCR01B, 0x0017040A
• write32 SDWCR10B, 0x31020707
• write32 SDWCR11B, 0x0017040A
• write32 SDDRVCR0B, 0x05555555
• write32 SDWCR2B, 0x30000000
• or_write32 SDPCRB, 0x00000080
• cmp_loop SDPCRB, 0x00000080, 0x00000080
• write32 SDGENCNTB, 0x00002710
• cmp_loop SDGENCNTB, 0xFFFFFFFF, 0x00000000
• write32 SDMRACR0B, 0x0000003F
• write32 SDMRB1, 0x00000000
• write32 SDGENCNTB, 0x000001F4
• cmp_loop SDGENCNTB, 0xFFFFFFFF, 0x00000000
• write32 SDMRACR0B, 0x0000FF0A
• write32 SDMRB3, 0x00000000
• write32 SDGENCNTB, 0x00000032
• cmp_loop SDGENCNTB, 0xFFFFFFFF, 0x00000000
• write32 SDMRACR0B, 0x00002201
• write32 SDMRB1, 0x00000000
• write32 SDMRACR0B, 0x00000402
• write32 SDMRB1, 0x00000000
• write32 SDMRACR0B, 0x00000403
• write32 SDMRB1, 0x00000000
• write32 SDMRB2, 0x00000000
• write32 SDMRTMPCRB, 0x88800004
• write32 SDMRTMPMSKB, 0x00000004
• write32 RTCORB, 0xA55A0032
• write32 RTCORHB, 0xA55A000C
• write32 RTCSRB, 0xA55A2048
• or_write32 SDCR0B, 0x00000800
• or_write32 SDCR1B, 0x00000400
• write32 ZQCCRB, 0xFFF20000
• or_write32 SDPDCR0B, 0x00030000
• write32 DPHYCNT1B, 0xA5390000
• write32 DPHYCNT0B, 0x00001200
• write32 DPHYCNT1B, 0x07CE0000
• write32 DPHYCNT0B, 0x00001247
• cmp_loop DPHYCNT2B, 0xFFFFFFFF, 0x07CE0000
• and_write32 SDPDCR0B, 0xFFFCFFFF
• write32 FRQCRD, 0x00000B0B
• cmp_loop FRQCRD, 0x80000000, 0x00000000

Can't all this be simplified by using tables?

• bx lr
• .pool
• .align 4

diff --git a/boards.cfg b/boards.cfg index 9ef903a..dfd9908 100644 --- a/boards.cfg +++ b/boards.cfg @@ -232,6 +232,7 @@ harmony arm armv7 harmony nvidia seaboard arm armv7 seaboard nvidia tegra2 ventana arm armv7 ventana nvidia tegra2 u8500_href arm armv7 u8500 st-ericsson u8500 +kzm_a9_gt arm armv7 kzm kmc rmobile actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 diff --git a/include/configs/kzm_a9_gt.h b/include/configs/kzm_a9_gt.h new file mode 100644 index 0000000..48b7afa --- /dev/null +++ b/include/configs/kzm_a9_gt.h @@ -0,0 +1,164 @@ +/*

• • Copyright (C) 2012 Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com
• • Copyright (C) 2012 Renesas Solutions Corp.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#ifndef __KZM_A9_GT_H +#define __KZM_A9_GT_H

+#undef DEBUG

+#define CONFIG_ARM_CORTEXA9 1

I think the "1" is unneeded; dito below.

+#define CONFIG_RMOBILE 1 +#define CONFIG_SH73A0 1 +#define CONFIG_KZM_A9_GT 1 +#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G

+#include <asm/arch/rmobile.h>

+#define CONFIG_ARCH_CPU_INIT 1 +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_L2_OFF 1

+#include <config_cmd_default.h> +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_CMD_FAT 1

+#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS "root=/dev/null console=ttySC4,115200" +#define CONFIG_INTEGRATOR 1 +#define CONFIG_ARCH_CINTEGRATOR 1 +#define CONFIG_BOOTDELAY 3

+#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS

+/* MEMORY */ +#define KZM_SDRAM_BASE (0x40000000) +#define PHYS_SDRAM KZM_SDRAM_BASE +#define PHYS_SDRAM_SIZE (512 * 1024 * 1024) +#define CONFIG_NR_DRAM_BANKS (1)

+/* NOR Flash */ +#define KZM_FLASH_BASE (0x00000000) +#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE) +#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) +#define CONFIG_SYS_MAX_FLASH_BANKS (1) +#define CONFIG_SYS_MAX_FLASH_SECT (512)

+/* prompt */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE 512 +#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }

+/* SCIF */ +#define CONFIG_SCIF_CONSOLE 1 +#define CONFIG_CONS_SCIF4 1 +#undef CONFIG_SYS_CONSOLE_INFO_QUIET +#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE

+#define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE) +#define CONFIG_SYS_MEMTEST_END \

• (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))

+#undef CONFIG_SYS_ALT_MEMTEST +#undef CONFIG_SYS_MEMTEST_SCRATCH +#undef CONFIG_SYS_LOADS_BAUD_CHANGE

+#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* MERAM */ +#define CONFIG_SYS_INIT_RAM_SIZE (0x00010000) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \

• 			 CONFIG_SYS_INIT_RAM_SIZE - \
  

• 			 GENERATED_GBL_DATA_SIZE)
  

+#define CONFIG_SYS_SDRAM_BASE KZM_SDRAM_BASE +#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)

+#define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#define CONFIG_SYS_GBL_DATA_SIZE (256) +#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)

+#define CONFIG_SYS_TEXT_BASE 0x00000000 +#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000

+/* FLASH */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#undef CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */ +#define CONFIG_ENV_SIZE FLASH_SECTOR_SIZE +#define CONFIG_ENV_OFFSET FLASH_SECTOR_SIZE +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)

+/* Timeout for Flash erase operations (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) +/* Timeout for Flash write operations (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) +/* Timeout for Flash set sector lock bit operations (in ms) */ +#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) +/* Timeout for Flash clear lock bit operations (in ms) */ +#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)

+#undef CONFIG_SYS_FLASH_PROTECTION +#undef CONFIG_SYS_DIRECT_FLASH_TFTP +#define CONFIG_ENV_IS_IN_FLASH

+/* GPIO / PFC */ +#define CONFIG_SH_GPIO_PFC 1

+/* Clock */ +#define CONFIG_SYS_CLK_FREQ 48000000 +#define CONFIG_SYS_CPU_CLK (1196000000) +#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ +#define CFG_HZ (1000) +#define CONFIG_SYS_HZ CFG_HZ

+/* Ether */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_BASE (0x10000000) +#define CONFIG_SMC911X_32_BIT 1

+/* I2C */ +#define CONFIG_CMD_I2C 1 +#define CONFIG_SH_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MULTI_BUS 1 +#define CONFIG_SYS_MAX_I2C_BUS 2 +#define CONFIG_SYS_I2C_MODULE 1 +#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK (41666666) +#define CONFIG_SH_I2C_BASE0 (0xE6820000) +#define CONFIG_SH_I2C_BASE1 (0xE6822000)

+#endif /* __KZM_A9_GT_H */

Amicalement,