Re: [U-Boot] [RFC PATCH 1/2] board: laird: add WB45N CPU module

On 07/07/2017 12:40, Ben Whitten wrote:

This board is based on the Atmel 9x5 eval board. Supporting the following features:

• Boot from NAND Flash
• Ethernet
• FIT
• SPL

Patch is assigned to me. However, this is Atmel, now orphaned. I haven't work with AT-91 since a very long time, so I cannot say more about patches, but it is a pity if the patches will be lost. Tom, should I merge them even if they are not i.MX related ? Or do you pick them yourself ?

Regards, Stefano

Signed-off-by: Ben Whitten ben.whitten@lairdtech.com Signed-off-by: Dan Kephart dan.kephart@lairdtech.com

---

arch/arm/mach-at91/Kconfig | 6 + arch/arm/mach-at91/include/mach/gpio.h | 2 + board/laird/wb45n/Kconfig | 12 ++ board/laird/wb45n/MAINTAINERS | 6 + board/laird/wb45n/Makefile | 6 + board/laird/wb45n/wb45n.c | 199 +++++++++++++++++++++++++++++++++ configs/wb45n_defconfig | 27 +++++ include/configs/wb45n.h | 163 +++++++++++++++++++++++++++ 8 files changed, 421 insertions(+) create mode 100644 board/laird/wb45n/Kconfig create mode 100644 board/laird/wb45n/MAINTAINERS create mode 100644 board/laird/wb45n/Makefile create mode 100644 board/laird/wb45n/wb45n.c create mode 100644 configs/wb45n_defconfig create mode 100644 include/configs/wb45n.h

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 99b88d1..e4d9690 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -164,6 +164,11 @@ config TARGET_VINCO select CPU_V7 select SUPPORT_SPL

+config TARGET_WB45N

• bool "Support Laird WB45N"
• select CPU_ARM926EJS
• select SUPPORT_SPL

endchoice

config SYS_SOC @@ -197,5 +202,6 @@ source "board/ronetix/pm9g45/Kconfig" source "board/siemens/corvus/Kconfig" source "board/siemens/taurus/Kconfig" source "board/siemens/smartweb/Kconfig" +source "board/laird/wb45n/Kconfig"

endif diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index df0f719..e206316 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -219,6 +219,8 @@ static inline unsigned pin_to_mask(unsigned pin) at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y) #define at91_set_B_periph(x, y) \ at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y) +#define at91_set_gpio_deglitch(x, y) \

• at91_set_pio_deglitch((x - PIN_BASE) / 32,(x % 32), y)

#define at91_set_gpio_output(x, y) \ at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y) #define at91_set_gpio_input(x, y) \ diff --git a/board/laird/wb45n/Kconfig b/board/laird/wb45n/Kconfig new file mode 100644 index 0000000..2a67337 --- /dev/null +++ b/board/laird/wb45n/Kconfig @@ -0,0 +1,12 @@ +if TARGET_WB45N

+config SYS_BOARD

• default "wb45n"

+config SYS_VENDOR

• default "laird"

+config SYS_CONFIG_NAME

• default "wb45n"

+endif diff --git a/board/laird/wb45n/MAINTAINERS b/board/laird/wb45n/MAINTAINERS new file mode 100644 index 0000000..60bb563 --- /dev/null +++ b/board/laird/wb45n/MAINTAINERS @@ -0,0 +1,6 @@ +WB45N CPU MODULE +M: Ben Whitten ben.whitten@lairdtech.com +S: Maintained +F: board/laird/wb45n/ +F: include/configs/wb45n.h +F: configs/wb45n_defconfig diff --git a/board/laird/wb45n/Makefile b/board/laird/wb45n/Makefile new file mode 100644 index 0000000..fc645dd --- /dev/null +++ b/board/laird/wb45n/Makefile @@ -0,0 +1,6 @@ +# +# +# SPDX-License-Identifier: GPL-2.0+ +#

+obj-y += wb45n.o diff --git a/board/laird/wb45n/wb45n.c b/board/laird/wb45n/wb45n.c new file mode 100644 index 0000000..5914071 --- /dev/null +++ b/board/laird/wb45n/wb45n.c @@ -0,0 +1,199 @@ +/*

• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91sam9x5_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <net.h> +#include <netdev.h>

+DECLARE_GLOBAL_DATA_PTR;

+/* ------------------------------------------------------------------------- */ +/*

• • Miscelaneous platform dependent initialisations
• */

+static void wb45n_nand_hw_init(void) +{

• struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
• struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
• unsigned long csa;
• csa = readl(&matrix->ebicsa);
• /* Enable CS3 */
• csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
• /* NAND flash on D0 */
• csa &= ~AT91_MATRIX_NFD0_ON_D16;
• writel(csa, &matrix->ebicsa);
• /* Configure SMC CS3 for NAND/SmartMedia */
• writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |

•       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  

•       &smc->cs[3].setup);
  

• writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |

•       AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
  

•       &smc->cs[3].pulse);
  

• writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),

•       &smc->cs[3].cycle);
  

• writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |

•       AT91_SMC_MODE_EXNW_DISABLE |
  

•       AT91_SMC_MODE_DBW_8 |
  

•       AT91_SMC_MODE_TDF_CYCLE(1), &smc->cs[3].mode);
  

• at91_periph_clk_enable(ATMEL_ID_PIOCD);
• /* Configure RDY/BSY */
• at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
• /* Enable NandFlash */
• at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
• /* Disable Flash Write Protect Line */
• at91_set_gpio_output(AT91_PIN_PD10, 1);
• at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
• at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
• at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
• at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */

+}

+static void wb45n_gpio_hw_init(void) +{

• /* Configure wifi gpio CHIP_PWD_L */
• at91_set_gpio_output(AT91_PIN_PA28, 0);
• /* Setup USB pins */
• at91_set_gpio_input(AT91_PIN_PB11, 0);
• at91_set_gpio_output(AT91_PIN_PB12, 0);
• /* IRQ pin, pullup, deglitch */
• at91_set_gpio_input(AT91_PIN_PB18, 1);
• at91_set_gpio_deglitch(AT91_PIN_PB18, 1);

+}

+int board_eth_init(bd_t *bis) +{

• int rc = 0;
• if (has_emac0())

• rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
  

• return rc;

+}

+int board_early_init_f(void) +{

• at91_seriald_hw_init();
• return 0;

+}

+int board_init(void) +{

• /* address of boot parameters */
• gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
• wb45n_gpio_hw_init();
• wb45n_nand_hw_init();
• at91_macb_hw_init();
• return 0;

+}

+int dram_init(void) +{

• gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,

•                            CONFIG_SYS_SDRAM_SIZE);
  

• return 0;

+}

+#if defined(CONFIG_SPL_BUILD) +#include <spl.h> +#include <nand.h>

+void at91_spl_board_init(void) +{

• /* Setup GPIO first */
• wb45n_gpio_hw_init();
• /* Bring up NAND */
• wb45n_nand_hw_init();

+}

+void matrix_init(void) +{

• struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
• unsigned long csa;
• csa = readl(&matrix->ebicsa);
• /* Pull ups on D0 - D16 */
• csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
• csa |= AT91_MATRIX_EBI_DBPD_OFF;
• /* Normal drive strength */
• csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
• /* Multi-port off */
• csa &= ~AT91_MATRIX_MP_ON;
• writel(csa, &matrix->ebicsa);

+}

+#include <asm/arch/atmel_mpddrc.h> +static void ddr2_conf(struct atmel_mpddrc_config *ddr2) +{

• ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM);
• ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |

•            ATMEL_MPDDRC_CR_NR_ROW_13 |
  

•            ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
  

•            ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
  

•            ATMEL_MPDDRC_CR_DQMS_SHARED);
  

• ddr2->rtr = 0x411;
• ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |

•              2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
  

•              2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
  

•              8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
  

•              2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
  

•              2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
  

•              2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
  

•              2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
  

• ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |

•              200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  

•              19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  

•              18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  

• ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |

•              2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  

•              3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  

•              7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  

•              2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  

+}

+void mem_init(void) +{

• struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
• struct atmel_mpddrc_config ddr2;
• unsigned long csa;
• ddr2_conf(&ddr2);
• /* enable DDR2 clock */
• at91_system_clk_enable(AT91_PMC_DDR);
• /* Chip select 1 is for DDR2/SDRAM */
• csa = readl(&matrix->ebicsa);
• csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
• writel(csa, &matrix->ebicsa);
• /* DDRAM2 Controller initialize */
• ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);

+} +#endif diff --git a/configs/wb45n_defconfig b/configs/wb45n_defconfig new file mode 100644 index 0000000..4ba0088 --- /dev/null +++ b/configs/wb45n_defconfig @@ -0,0 +1,27 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_WB45N=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_LZMA=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/wb45n.h b/include/configs/wb45n.h new file mode 100644 index 0000000..fd714dd --- /dev/null +++ b/include/configs/wb45n.h @@ -0,0 +1,163 @@ +/*

• • Configuation settings for the WB45N CPU Module.
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef __CONFIG_H__ +#define __CONFIG_H__

+#include <asm/hardware.h>

+#define CONFIG_SYS_TEXT_BASE 0x23f00000

+/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */

+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT

+/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +#define CONFIG_AT91_GPIO

+/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS

+/*

• • BOOTP options
• */

+#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME

+/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */

+#define CONFIG_SYS_INIT_SP_ADDR \

• (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)

+/* NAND flash */ +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5

+/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC 1 +#define CONFIG_ATMEL_NAND_HW_PMECC 1 +#define CONFIG_PMECC_CAP 4 +#define CONFIG_PMECC_SECTOR_SIZE 512

+#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_RBTREE +#define CONFIG_LZO

+/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY +#define CONFIG_ETHADDR C0:EE:40:00:00:00 +#define CONFIG_ENV_OVERWRITE 1

+/* System */ +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END 0x23e00000

+#ifdef CONFIG_SYS_USE_NANDFLASH +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0xa0000 +#define CONFIG_ENV_OFFSET_REDUND 0xc0000 +#define CONFIG_ENV_SIZE 0x20000 /* 1 block = 128 kB */

+#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xe0000 0x280000; " \

• "run _mtd; bootm"

+#define MTDIDS_DEFAULT "nand0=atmel_nand" +#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:" \

•                        "128K(at91bs)," \
  

•                        "512K(u-boot)," \
  

•                        "128K(u-boot-env)," \
  

•                        "128K(redund-env)," \
  

•                        "2560K(kernel-a)," \
  

•                        "2560K(kernel-b)," \
  

•                        "38912K(rootfs-a)," \
  

•                        "38912K(rootfs-b)," \
  

•                        "46208K(user)," \
  

•                        "512K(logs)"
  

+#else +#error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH' +#endif

+#define CONFIG_BOOTARGS "console=ttyS0,115200 earlyprintk " \

•                        "rw noinitrd mem=64M "              \
  

•                        "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=6"
  

+#define CONFIG_EXTRA_ENV_SETTINGS \

• "_mtd=mtdparts default; set bootargs ${bootargs} ${mtdparts}\0" \
• "autoload=no\0" \
• "autostart=no\0" \
• "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
• "\0"

+#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE

+/*

• • Size of malloc() pool
• */

+#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)

+/* SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE 0x6000 +#define CONFIG_SPL_STACK 0x308000

+#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000

+#define CONFIG_SYS_MONITOR_LEN (512 << 10)

+#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302

+#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER

+#endif /* __CONFIG_H__ */