
20 Nov
2019
20 Nov
'19
4 a.m.
Hi Suneel,
On Tue, 29 Oct 2019 at 14:08, Suneel Garapati suneelglinux@gmail.com wrote:
From: Suneel Garapati sgarapati@marvell.com
For SATA controller found on OcteonTX SoC's, use non-standard PCI BAR0 instead of BAR5.
Signed-off-by: Suneel Garapati sgarapati@marvell.com
drivers/ata/ahci.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 5f929700c0..f8fd2043e3 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -1193,10 +1193,17 @@ int ahci_probe_scsi(struct udevice *ahci_dev, ulong base) int ahci_probe_scsi_pci(struct udevice *ahci_dev) { ulong base;
u16 vendor, device; base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5, PCI_REGION_MEM);
dm_pci_read_config16(ahci_dev, PCI_VENDOR_ID, &vendor);
dm_pci_read_config16(ahci_dev, PCI_DEVICE_ID, &device);
if (vendor == 0x177d && device == 0xa01c)
This should use constants from pci_ids.h
base = (uintptr_t)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_0,
PCI_REGION_MEM); return ahci_probe_scsi(ahci_dev, base);
}
#endif
2.23.0
Regards, Simon