On Tue, Aug 06, 2019 at 04:08:42PM +0530, Keerthy wrote:
ICSSG2 provide dual Gigabit Ethernet support. Currently mdio clock is part of this node and also the icssg2_rgmii_pins_default pinmux node has the mdio pins as there is no davinci mdio driver.
Currently icssg2 instances are supported. Either mii0 or mii1 can be enabled at a time.
Signed-off-by: Keerthy j-keerthy@ti.com
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 118 +++++++++++++++++++ 1 file changed, 118 insertions(+)
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index 71a7069e74..53399dfff6 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -16,6 +16,63 @@ serial2 = &main_uart0; ethernet0 = &cpsw_port1; };
- /* Dual Ethernet application node on PRU-ICSSG2 */
- pruss2_eth: pruss2_eth {
compatible = "ti,am654-icssg-prueth";pinctrl-names = "default";pinctrl-0 = <&icssg2_rgmii_pins_default>;sram = <&icssg2_sram>;clocks = <&k3_clks 64 3>;clock-names = "mdio_fck";u-boot,dm-spl;prus = <&pru2_0>, <&rtu2_0>, <&pru2_1>, <&rtu2_1>;firmware-name = "ti-pruss/am65x-pru0-prueth-fw.elf","ti-pruss/am65x-rtu0-prueth-fw.elf","ti-pruss/am65x-pru1-prueth-fw.elf","ti-pruss/am65x-rtu1-prueth-fw.elf";mii-g-rt = <&icssg2_mii_g_rt>;dma-coherent;dmas = <&mcu_udmap &icssg2 0 UDMA_DIR_TX>, /* egress slice 0 */<&mcu_udmap &icssg2 1 UDMA_DIR_TX>, /* egress slice 0 */<&mcu_udmap &icssg2 2 UDMA_DIR_TX>, /* egress slice 0 */<&mcu_udmap &icssg2 3 UDMA_DIR_TX>, /* mgmnt cmd slice 0 */<&mcu_udmap &icssg2 4 UDMA_DIR_TX>, /* egress slice 1 */<&mcu_udmap &icssg2 5 UDMA_DIR_TX>, /* egress slice 1 */<&mcu_udmap &icssg2 6 UDMA_DIR_TX>, /* egress slice 1 */<&mcu_udmap &icssg2 7 UDMA_DIR_TX>, /* mgmnt cmd slice 1 */<&mcu_udmap &icssg2 0 UDMA_DIR_RX>, /* ingress slice 0 */<&mcu_udmap &icssg2 1 UDMA_DIR_RX>, /* ingress slice 1 */<&mcu_udmap &icssg2 2 UDMA_DIR_RX>, /* mgmnt rsp slice 0 */<&mcu_udmap &icssg2 3 UDMA_DIR_RX>; /* mgmnt rsp slice 1 */dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3","tx1-0", "tx1-1", "tx1-2", "tx1-3","rx0", "rx1","rxmgm0", "rxmgm1";pruss2_emac0: ethernet-mii0 {phy-handle = <&pruss2_eth0_phy>;phy-mode = "rgmii-id";syscon-rgmii-delay = <&scm_conf 0x4120>;/* Filled in by bootloader */local-mac-address = [00 00 00 00 00 00];};+/*
- Commenting out the second mii interface as the framework
- supports one interface in a single probe
- So either mii1 or mii2 can be used. In case mii1 is needed
- uncomment mii1 and comment out mii0
pruss2_emac1: ethernet-mii1 {phy-handle = <&pruss2_eth1_phy>;phy-mode = "rgmii-id";syscon-rgmii-delay = <&scm_conf 0x4124>;local-mac-address = [00 00 00 00 00 00];};+*/
- };
};
&cbass_main{ @@ -274,6 +331,47 @@ u-boot,dm-spl; };
- icssg2_rgmii_pins_default: icssg2_rgmii_pins_default {
pinctrl-single,pins = <AM65X_IOPAD(0x00ac, PIN_INPUT , 2) /* (AH15) PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */
Why are there spaces behind the pin direction definitions (PIN_INPUT[space], ...)? I've never seen that before. The pinmix definitions are supposed to be a 1:1 copy from our AM64x pinmux tool for consistency sake. Is the pinmux tool broken?
-- Andreas Dannenberg Texas Instruments Inc
AM65X_IOPAD(0x00b0, PIN_INPUT , 2) /* (AC16) PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */AM65X_IOPAD(0x00b4, PIN_INPUT , 2) /* (AD17) PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */AM65X_IOPAD(0x00b8, PIN_INPUT , 2) /* (AH14) PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */AM65X_IOPAD(0x00cc, PIN_OUTPUT , 2) /* (AD15) PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */AM65X_IOPAD(0x00d0, PIN_OUTPUT , 2) /* (AF14) PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */AM65X_IOPAD(0x00d4, PIN_OUTPUT , 2) /* (AC15) PRG2_PRU1_GPO10.PRG2_RGMII2_TD2 */AM65X_IOPAD(0x00d8, PIN_OUTPUT , 2) /* (AD14) PRG2_PRU1_GPO11.PRG2_RGMII2_TD3 */AM65X_IOPAD(0x00dc, PIN_INPUT , 2) /* (AE14) PRG2_PRU1_GPO16.PRG2_RGMII2_TXC */AM65X_IOPAD(0x00c4, PIN_OUTPUT , 2) /* (AC17) PRG2_PRU1_GPO6.PRG2_RGMII2_TX_CTL */AM65X_IOPAD(0x00c0, PIN_INPUT , 2) /* (AG15) PRG2_PRU1_GPO5.PRG2_RGMII2_RXC */AM65X_IOPAD(0x00bc, PIN_INPUT , 2) /* (AG14) PRG2_PRU1_GPO4.PRG2_RGMII2_RX_CTL */AM65X_IOPAD(0x0078, PIN_INPUT , 2) /* (AF18) PRG2_PRU0_GPO0.PRG2_RGMII1_RD0 */AM65X_IOPAD(0x007c, PIN_INPUT , 2) /* (AE18) PRG2_PRU0_GPO1.PRG2_RGMII1_RD1 */AM65X_IOPAD(0x0080, PIN_INPUT , 2) /* (AH17) PRG2_PRU0_GPO2.PRG2_RGMII1_RD2 */AM65X_IOPAD(0x0084, PIN_INPUT , 2) /* (AG18) PRG2_PRU0_GPO3.PRG2_RGMII1_RD3 */AM65X_IOPAD(0x0098, PIN_OUTPUT , 2) /* (AH16) PRG2_PRU0_GPO8.PRG2_RGMII1_TD0 */AM65X_IOPAD(0x009c, PIN_OUTPUT , 2) /* (AG16) PRG2_PRU0_GPO9.PRG2_RGMII1_TD1 */AM65X_IOPAD(0x00a0, PIN_OUTPUT , 2) /* (AF16) PRG2_PRU0_GPO10.PRG2_RGMII1_TD2 */AM65X_IOPAD(0x00a4, PIN_OUTPUT , 2) /* (AE16) PRG2_PRU0_GPO11.PRG2_RGMII1_TD3 */AM65X_IOPAD(0x00a8, PIN_INPUT , 2) /* (AD16) PRG2_PRU0_GPO16.PRG2_RGMII1_TXC */AM65X_IOPAD(0x0090, PIN_OUTPUT , 2) /* (AE17) PRG2_PRU0_GPO6.PRG2_RGMII1_TX_CTL */AM65X_IOPAD(0x008c, PIN_INPUT , 2) /* (AF17) PRG2_PRU0_GPO5.PRG2_RGMII1_RXC */AM65X_IOPAD(0x0088, PIN_INPUT , 2) /* (AG17) PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL *//* HACK to get MDIO Pins in the right state */AM65X_IOPAD(0x0094, PIN_INPUT , 2) /* (AC19) PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */AM65X_IOPAD(0x00c8, PIN_OUTPUT , 2) /* (AE15) PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */>;u-boot,dm-spl;- };
- icssg2_mdio_pins_default: icssg2_mdio_pins_default {
pinctrl-single,pins = <AM65X_IOPAD(0x0094, PIN_INPUT , 2) /* (AC19) PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */AM65X_IOPAD(0x00c8, PIN_OUTPUT , 2) /* (AE15) PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */>;u-boot,dm-spl;- };
};
&main_pmx1 { @@ -373,3 +471,23 @@ reg = <0x60000 0x10000>; }; };
+&icssg2_mdio{
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&icssg2_mdio_pins_default>;
- pruss2_eth0_phy: ethernet-phy@0 {
reg = <0>;ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;- };
- pruss2_eth1_phy: ethernet-phy@3 {
reg = <3>;ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;- };
+};
2.17.1
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot