On Fri 20 Dec 2019 at 19:47, Anand Moon linux.amoon@gmail.com wrote:
Hi Neil, + Jerome,
On Sat, 21 Dec 2019 at 00:28, Anand Moon linux.amoon@gmail.com wrote:
Hi Neil,
Could you try the following patches instead of this one ?
https://patchwork.ozlabs.org/patch/1213648/ https://patchwork.ozlabs.org/patch/1213650/
Yes I have tried this series it worked for me. It's much better fix than my approach.
Looks like I did some wrong testing, with microSD card connected, I missed that. For me at this point this issue persist. Here is the logs below.
emmc switch 1 ok 00000000 emmc switch 2 ok fastboot data verify verify result: 255 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from eMMC, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 00000000 emmc switch 0 ok Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from eMMC, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully!
R0_RxClkDly_Margin==82 ps 7 R0_TxDqDly_Margi==106 ps 9
R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0
dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==435 bdlr_100_min==435 bdlr_100_max==435 bdlr_100_cur==435 aft test bdlr_100_average==435 bdlr_100_min==435 bdlr_100_max==435 bdlr_100_cur==435 non-sec scramble use zero key ddr scramble enabled
100bdlr_step_size ps== 435 result report boot times 2Enable ddr reg access 00000000 emmc switch 3 ok Authentication key not yet programmed get rpmb counter error 0x00000007 00000000 emmc switch 0 ok Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from eMMC, src: 0x0006c200, des: 0x0175c000, size: 0x00088200, part: 0 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [Image: g12b_v1.1.3375-8f9c8a7 2019-01-24 10:44:46 guotai.shen@droid11-sz] OPS=0x40 ring efuse init chipver efuse init 29 0a 40 00 01 20 10 00 00 15 30 32 54 52 4d 50 [3.472682 Inits done] secure task start! high task start! low task start! run into bl31 NOTICE: BL31: v1.3(release):ab8811b NOTICE: BL31: Built : 15:03:31, Feb 12 2019 NOTICE: BL31: G12A normal boot! NOTICE: BL31: BL33 decompress pass ERROR: Error initializing runtime service opteed_fast
U-Boot 2020.01-rc5-00009-g269c6e8c39 (Dec 20 2019 - 15:38:58 +0530) odroid-n2
Model: Hardkernel ODROID-N2 SoC: Amlogic Meson G12B (S922X) Revision 29:a (40:2) DRAM: 3.8 GiB MMC: sd@ffe05000: 0, mmc@ffe07000: 1 In: serial@3000 Out: serial@3000 Err: serial@3000 Net: Warning: ethernet@ff3f0000 (eth0) using random MAC address - 4a:ab:15:ba:29:62 eth0: ethernet@ff3f0000 Hit any key to stop autoboot: 0 Card did not respond to voltage select! unable to select a mode switch to partitions #0, OK mmc1(part 0) is current device ** No partition table - mmc 1 ** MMC Device 2 not found no mmc device at slot 2 starting USB... Bus usb@ff500000: Register 3000140 NbrPorts 3 Starting the controller USB XHCI 1.10 scanning bus usb@ff500000 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found
complete logs in below linked. [0] http://pastebin.com/UsVMYAvW
-Anand
I'm not quite sure I get what I should understand from this log.
I can comment on the original patch though.
I think you should keep the phase settings aligned with Linux.
A) Among the exchange I had with amlogic, I got that there should always be a phase shift of 180 degree between the core and Tx phase.
B) So far, Core=180, Tx=0, Rx=0 has proven to be quite stable for all the devices. I spent significant amount of time testing that.
If that's not the case for the N2 under linux, please report it to the related ML. If these settings works under Linux, then it is not the problem and I don't think you should change them in u-boot.