This set is to change MMU tables so DDR is in non-secure mode that non-secure master such as SDHC DMA can access the data. To mix secure and non-secure MMU entries, the MMU tables themselves have to be in secure memory. A small portion memory is reserved at the end of DDR (before debug server and MC) to host secure application and the MMU tables.
This is different from existing armv7 secure_ram_addr() solution. U-boot can run in the middle of memory if the memory is large. Having security memory at the very end simplifies MMU setup.
This is RFC patch, verified on LS2085AQDS only.
Changes in v3: Put ifdef around secure_ram Move defining CONFIG_SYS_MEM_RESERVE_SECURE to patch 2/2 Replace CONFIG_FSL_PPA_RESERVED_DRAM_SIZE with CONFIG_SYS_MEM_RESERVE_SECURE Sanity check gd->secure_ram before using Define CONFIG_SYS_MEM_RESERVE_SECURE in SoC header file Include ls1043ardb Modified commit message.
Changes in v2: Do not use CONFIG_SYS_MEM_TOP_HIDE mechanism Move gd->arch.secure_ram to gd->secure_ram. Change the calculation of gd->secure_ram accordingly. Chnage commit message slightly accordingly.
Changes in v1: Initial patch. Depends on http://patchwork.ozlabs.org/patch/540248/
York Sun (2): Reserve secure memory armv8: fsl-layerscape: Make DDR non secure in MMU tables
README | 8 ++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 146 +++++++++++++++++++-- arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 + arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 12 +- board/freescale/ls1043ardb/ddr.c | 4 + board/freescale/ls2085a/ddr.c | 15 +++ board/freescale/ls2085aqds/ddr.c | 15 +++ board/freescale/ls2085ardb/ddr.c | 15 +++ common/board_f.c | 9 ++ common/cmd_bdinfo.c | 4 + include/asm-generic/global_data.h | 13 ++ 11 files changed, 233 insertions(+), 14 deletions(-)