Add the support of SYSCFG clock used by syscon driver to prepare the clock management of STM32MP_SYSCON_SYSCFG.
This clock is already defined in kernel device tree, stm32mp151.dtsi but not yet supported in the syscon driver:
syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>; clocks = <&rcc SYSCFG>; };
It is safe to support this clock in U-Boot driver with RCC_MC_APB3ENSETR, Bit 11 SYSCFGEN: SYSCFG peripheral clocks enable.
Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com ---
drivers/clk/clk_stm32mp1.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 0c0ef366a1..48c9514ba0 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -540,6 +540,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3), + STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q), STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),