[U-Boot] [PATCH 10/11] imx: imx7d: initial arch level support

* Introduce a new cpu type MXC_CPU_MX7D and relevant functions for mx7d. Implement the soc.c for various system level functions like: temperature check, arch init, get mac fuse, boot mode get/apply, etc. * Additional, enable building imx common platform files for mx7d.

Signed-off-by: Adrian Alonso aalonso@freescale.com Signed-off-by: Peng Fan Peng.Fan@freescale.com Signed-off-by: Ye.Li B37916@freescale.com --- arch/arm/Kconfig | 7 + arch/arm/Makefile | 4 +- arch/arm/cpu/armv7/Makefile | 3 +- arch/arm/cpu/armv7/mx7/Makefile | 9 + arch/arm/cpu/armv7/mx7/clock.c | 1130 +++++++++++ arch/arm/cpu/armv7/mx7/clock_slice.c | 757 +++++++ arch/arm/cpu/armv7/mx7/hab.c | 277 +++ arch/arm/cpu/armv7/mx7/soc.c | 409 ++++ arch/arm/imx-common/Makefile | 17 +- arch/arm/imx-common/cpu.c | 17 + arch/arm/imx-common/timer.c | 9 +- arch/arm/include/asm/arch-imx/cpu.h | 1 + arch/arm/include/asm/arch-mx7/clock.h | 348 ++++ arch/arm/include/asm/arch-mx7/clock_slice.h | 116 ++ arch/arm/include/asm/arch-mx7/crm_regs.h | 2813 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx7/gpio.h | 12 + arch/arm/include/asm/arch-mx7/hab.h | 69 + arch/arm/include/asm/arch-mx7/imx-regs.h | 1303 +++++++++++++ arch/arm/include/asm/arch-mx7/mx7-pins.h | 19 + arch/arm/include/asm/arch-mx7/mx7d_pins.h | 1308 +++++++++++++ arch/arm/include/asm/arch-mx7/sys_proto.h | 45 + arch/arm/include/asm/imx-common/boot_mode.h | 21 + drivers/watchdog/Makefile | 2 +- 23 files changed, 8688 insertions(+), 8 deletions(-) create mode 100644 arch/arm/cpu/armv7/mx7/Makefile create mode 100644 arch/arm/cpu/armv7/mx7/clock.c create mode 100644 arch/arm/cpu/armv7/mx7/clock_slice.c create mode 100644 arch/arm/cpu/armv7/mx7/hab.c create mode 100644 arch/arm/cpu/armv7/mx7/soc.c create mode 100644 arch/arm/include/asm/arch-mx7/clock.h create mode 100644 arch/arm/include/asm/arch-mx7/clock_slice.h create mode 100644 arch/arm/include/asm/arch-mx7/crm_regs.h create mode 100644 arch/arm/include/asm/arch-mx7/gpio.h create mode 100644 arch/arm/include/asm/arch-mx7/hab.h create mode 100644 arch/arm/include/asm/arch-mx7/imx-regs.h create mode 100644 arch/arm/include/asm/arch-mx7/mx7-pins.h create mode 100644 arch/arm/include/asm/arch-mx7/mx7d_pins.h create mode 100644 arch/arm/include/asm/arch-mx7/sys_proto.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 506463c..40aabb6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -578,6 +578,12 @@ config TARGET_MX6SXSABRESD select DM select DM_THERMAL

+config TARGET_MX7DSABRESD + bool "Support mx7dsabresd" + select CPU_V7 + select DM + select DM_THERMAL + config TARGET_GW_VENTANA bool "Support gw_ventana" select CPU_V7 @@ -923,6 +929,7 @@ source "board/freescale/mx6qsabreauto/Kconfig" source "board/freescale/mx6sabresd/Kconfig" source "board/freescale/mx6slevk/Kconfig" source "board/freescale/mx6sxsabresd/Kconfig" +source "board/freescale/mx7dsabresd/Kconfig" source "board/freescale/vf610twr/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/genesi/mx51_efikamx/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 6f30098..6708140 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -78,11 +78,11 @@ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/

ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35)) +ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35)) libs-y += arch/arm/imx-common/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35 mxs vf610)) libs-y += arch/arm/imx-common/ endif endif diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 5a76100..8defb1b 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,7 +12,7 @@ obj-y += cache_v7.o obj-y += cpu.o cp15.o obj-y += syslib.o

-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),) ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif @@ -45,6 +45,7 @@ obj-$(CONFIG_ARCH_EXYNOS) += exynos/ obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/ obj-$(if $(filter mx5,$(SOC)),y) += mx5/ obj-$(CONFIG_MX6) += mx6/ +obj-$(CONFIG_MX7) += mx7/ obj-$(CONFIG_OMAP34XX) += omap3/ obj-$(CONFIG_OMAP44XX) += omap4/ obj-$(CONFIG_OMAP54XX) += omap5/ diff --git a/arch/arm/cpu/armv7/mx7/Makefile b/arch/arm/cpu/armv7/mx7/Makefile new file mode 100644 index 0000000..d36501d --- /dev/null +++ b/arch/arm/cpu/armv7/mx7/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# +# + +obj-y := soc.o clock.o clock_slice.o +obj-$(CONFIG_SECURE_BOOT) += hab.o diff --git a/arch/arm/cpu/armv7/mx7/clock.c b/arch/arm/cpu/armv7/mx7/clock.c new file mode 100644 index 0000000..fe92de9 --- /dev/null +++ b/arch/arm/cpu/armv7/mx7/clock.c @@ -0,0 +1,1130 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Author: + * Peng Fan Peng.Fan@freescale.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <div64.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> + +struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) + ANATOP_BASE_ADDR; +struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + +#ifdef CONFIG_FSL_ESDHC +DECLARE_GLOBAL_DATA_PTR; +#endif + +int get_clocks(void) +{ +#ifdef CONFIG_FSL_ESDHC +#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR + gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); +#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR + gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); +#else + gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); +#endif +#endif + return 0; +} + +u32 get_ahb_clk(void) +{ + return get_root_clk(AHB_CLK_ROOT); +} + +static u32 get_ipg_clk(void) +{ + /* + * The AHB and IPG are fixed at 2:1 ratio, and synchronized to + * each other. + */ + return get_ahb_clk() / 2; +} + +u32 imx_get_uartclk(void) +{ + return get_root_clk(UART1_CLK_ROOT); +} + +u32 imx_get_fecclk(void) +{ + return get_root_clk(ENET_AXI_CLK_ROOT); +} + +#ifdef CONFIG_MXC_OCOTP +void enable_ocotp_clk(unsigned char enable) +{ + clock_enable(CCGR_OCOTP, enable); +} + +void enable_thermal_clk(void) +{ + enable_ocotp_clk(1); +} +#endif + +void enable_usboh3_clk(unsigned char enable) +{ + u32 target; + + if (enable) { + /* disable the clock gate first */ + clock_enable(CCGR_USB_HSIC, 0); + + /* 120Mhz */ + target = CLK_ROOT_ON | USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(USB_HSIC_CLK_ROOT, target); + + /* enable the clock gate */ + clock_enable(CCGR_USB_CTRL, 1); + clock_enable(CCGR_USB_HSIC, 1); + clock_enable(CCGR_USB_PHY1, 1); + clock_enable(CCGR_USB_PHY2, 1); + } else { + clock_enable(CCGR_USB_CTRL, 0); + clock_enable(CCGR_USB_HSIC, 0); + clock_enable(CCGR_USB_PHY1, 0); + clock_enable(CCGR_USB_PHY2, 0); + } + +} + +static u32 decode_pll(enum pll_clocks pll, u32 infreq) +{ + u32 reg, div_sel; + u32 num, denom; + + /* + * Alought there are four choices for the bypass src, + * we choose OSC_24M which is the default set in ROM. + */ + switch (pll) { + case PLL_CORE: + reg = readl(&ccm_anatop->pll_arm); + + if (reg & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK) + return 0; + + if (reg & CCM_ANALOG_PLL_ARM_BYPASS_MASK) + return MXC_HCLK; + + div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT; + + return (infreq * div_sel) / 2; + + case PLL_SYS: + reg = readl(&ccm_anatop->pll_480); + + if (reg & CCM_ANALOG_PLL_480_POWERDOWN_MASK) + return 0; + + if (reg & CCM_ANALOG_PLL_480_BYPASS_MASK) + return MXC_HCLK; + + if (((reg & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT) == 0) + return 480000000u; + else + return 528000000u; + + case PLL_ENET: + reg = readl(&ccm_anatop->pll_enet); + + if (reg & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK) + return 0; + + if (reg & CCM_ANALOG_PLL_ENET_BYPASS_MASK) + return MXC_HCLK; + + return 1000000000u; + + case PLL_DDR: + reg = readl(&ccm_anatop->pll_ddr); + + if (reg & CCM_ANALOG_PLL_DDR_POWERDOWN_MASK) + return 0; + + num = ccm_anatop->pll_ddr_num; + denom = ccm_anatop->pll_ddr_denom; + + if (reg & CCM_ANALOG_PLL_DDR_BYPASS_MASK) + return MXC_HCLK; + + div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT; + + return infreq * (div_sel + num / denom); + + case PLL_USB: + return 480000000u; + + default: + printf("Unsupported pll clocks %d\n", pll); + break; + } + + return 0; +} + +static u32 mxc_get_pll_sys_derive(int derive) +{ + u32 freq, div, frac; + u32 reg; + + div = 1; + reg = readl(&ccm_anatop->pll_480); + freq = decode_pll(PLL_SYS, MXC_HCLK); + + switch (derive) { + case PLL_SYS_MAIN_480M_CLK: + if (reg & CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK) + return 0; + else + return freq; + case PLL_SYS_MAIN_240M_CLK: + if (reg & CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK) + return 0; + else + return freq / 2; + case PLL_SYS_MAIN_120M_CLK: + if (reg & CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK) + return 0; + else + return freq / 4; + case PLL_SYS_PFD0_392M_CLK: + reg = readl(&ccm_anatop->pfd_480a); + if (reg & CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK) + return 0; + frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >> + CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT; + break; + case PLL_SYS_PFD0_196M_CLK: + if (reg & CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK) + return 0; + reg = readl(&ccm_anatop->pfd_480a); + frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >> + CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT; + div = 2; + break; + case PLL_SYS_PFD1_332M_CLK: + reg = readl(&ccm_anatop->pfd_480a); + if (reg & CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK) + return 0; + frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >> + CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT; + break; + case PLL_SYS_PFD1_166M_CLK: + if (reg & CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK) + return 0; + reg = readl(&ccm_anatop->pfd_480a); + frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >> + CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT; + div = 2; + break; + case PLL_SYS_PFD2_270M_CLK: + reg = readl(&ccm_anatop->pfd_480a); + if (reg & CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK) + return 0; + frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >> + CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT; + break; + case PLL_SYS_PFD2_135M_CLK: + if (reg & CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK) + return 0; + reg = readl(&ccm_anatop->pfd_480a); + frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >> + CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT; + div = 2; + break; + case PLL_SYS_PFD3_CLK: + reg = readl(&ccm_anatop->pfd_480a); + if (reg & CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK) + return 0; + frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >> + CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT; + break; + case PLL_SYS_PFD4_CLK: + reg = readl(&ccm_anatop->pfd_480b); + if (reg & CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK) + return 0; + frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >> + CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT; + break; + case PLL_SYS_PFD5_CLK: + reg = readl(&ccm_anatop->pfd_480b); + if (reg & CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK) + return 0; + frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >> + CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT; + break; + case PLL_SYS_PFD6_CLK: + reg = readl(&ccm_anatop->pfd_480b); + if (reg & CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK) + return 0; + frac = (reg & CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK) >> + CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT; + break; + case PLL_SYS_PFD7_CLK: + reg = readl(&ccm_anatop->pfd_480b); + if (reg & CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK) + return 0; + frac = (reg & CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK) >> + CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT; + break; + default: + printf("Error derived pll_sys clock %d\n", derive); + return 0; + } + + return ((freq / frac) * 18) / div; +} + +static u32 mxc_get_pll_enet_derive(int derive) +{ + u32 freq, reg; + + freq = decode_pll(PLL_ENET, MXC_HCLK); + reg = readl(&ccm_anatop->pll_enet); + + switch (derive) { + case PLL_ENET_MAIN_500M_CLK: + if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK) + return freq / 2; + break; + case PLL_ENET_MAIN_250M_CLK: + if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK) + return freq / 4; + break; + case PLL_ENET_MAIN_125M_CLK: + if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK) + return freq / 8; + break; + case PLL_ENET_MAIN_100M_CLK: + if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK) + return freq / 10; + break; + case PLL_ENET_MAIN_50M_CLK: + if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK) + return freq / 20; + break; + case PLL_ENET_MAIN_40M_CLK: + if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK) + return freq / 25; + break; + case PLL_ENET_MAIN_25M_CLK: + if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK) + return freq / 40; + break; + default: + printf("Error derived pll_enet clock %d\n", derive); + break; + } + + return 0; +} + +static u32 mxc_get_pll_ddr_derive(int derive) +{ + u32 freq, reg; + + freq = decode_pll(PLL_DDR, MXC_HCLK); + reg = readl(&ccm_anatop->pll_ddr); + + switch (derive) { + case PLL_DRAM_MAIN_1066M_CLK: + return freq; + case PLL_DRAM_MAIN_533M_CLK: + if (reg & CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK) + return freq / 2; + break; + default: + printf("Error derived pll_ddr clock %d\n", derive); + break; + } + + return 0; +} + +static u32 mxc_get_pll_derive(enum pll_clocks pll, int derive) +{ + switch (pll) { + case PLL_SYS: + return mxc_get_pll_sys_derive(derive); + case PLL_ENET: + return mxc_get_pll_enet_derive(derive); + case PLL_DDR: + return mxc_get_pll_ddr_derive(derive); + default: + printf("Error pll.\n"); + return 0; + } +} + +static u32 get_root_src_clk(enum clk_root_src root_src) +{ + switch (root_src) { + case OSC_24M_CLK: + return 24000000u; + case PLL_ARM_MAIN_800M_CLK: + return decode_pll(PLL_CORE, MXC_HCLK); + + case PLL_SYS_MAIN_480M_CLK: + case PLL_SYS_MAIN_240M_CLK: + case PLL_SYS_MAIN_120M_CLK: + case PLL_SYS_PFD0_392M_CLK: + case PLL_SYS_PFD0_196M_CLK: + case PLL_SYS_PFD1_332M_CLK: + case PLL_SYS_PFD1_166M_CLK: + case PLL_SYS_PFD2_270M_CLK: + case PLL_SYS_PFD2_135M_CLK: + case PLL_SYS_PFD3_CLK: + case PLL_SYS_PFD4_CLK: + case PLL_SYS_PFD5_CLK: + case PLL_SYS_PFD6_CLK: + case PLL_SYS_PFD7_CLK: + return mxc_get_pll_derive(PLL_SYS, root_src); + + case PLL_ENET_MAIN_500M_CLK: + case PLL_ENET_MAIN_250M_CLK: + case PLL_ENET_MAIN_125M_CLK: + case PLL_ENET_MAIN_100M_CLK: + case PLL_ENET_MAIN_50M_CLK: + case PLL_ENET_MAIN_40M_CLK: + case PLL_ENET_MAIN_25M_CLK: + return mxc_get_pll_derive(PLL_ENET, root_src); + + case PLL_DRAM_MAIN_1066M_CLK: + case PLL_DRAM_MAIN_533M_CLK: + return mxc_get_pll_derive(PLL_DDR, root_src); + + case PLL_AUDIO_MAIN_CLK: + return decode_pll(PLL_AUDIO, MXC_HCLK); + case PLL_VIDEO_MAIN_CLK: + return decode_pll(PLL_VIDEO, MXC_HCLK); + + case PLL_USB_MAIN_480M_CLK: + return decode_pll(PLL_USB, MXC_HCLK); + + case REF_1M_CLK: + return 1000000; + case OSC_32K_CLK: + return MXC_CLK32; + + case EXT_CLK_1: + case EXT_CLK_2: + case EXT_CLK_3: + case EXT_CLK_4: + printf("No EXT CLK supported??\n"); + break; + }; + + return 0; +} + +u32 get_root_clk(enum clk_root_index clock_id) +{ + enum clk_root_src root_src; + u32 post_podf, pre_podf, auto_podf, root_src_clk; + int auto_en; + + if (clock_root_enabled(clock_id) <= 0) + return 0; + + if (clock_get_prediv(clock_id, &pre_podf) < 0) + return 0; + + if (clock_get_postdiv(clock_id, &post_podf) < 0) + return 0; + + if (clock_get_autopostdiv(clock_id, &auto_podf, &auto_en) < 0) + return 0; + + if (auto_en == 0) + auto_podf = 0; + + if (clock_get_src(clock_id, &root_src) < 0) + return 0; + + root_src_clk = get_root_src_clk(root_src); + + /* + * bypass clk is ignored. + */ + + return root_src_clk / (post_podf + 1) / (pre_podf + 1) / + (auto_podf + 1); +} + +static u32 get_ddrc_clk(void) +{ + u32 reg, freq; + enum root_post_div post_div; + + reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root); + if (reg & CLK_ROOT_MUX_MASK) + /* DRAM_ALT_CLK_ROOT */ + freq = get_root_clk(DRAM_ALT_CLK_ROOT); + else + /* PLL_DRAM_MAIN_1066M_CLK */ + freq = mxc_get_pll_derive(PLL_DDR, PLL_DRAM_MAIN_1066M_CLK); + + post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK; + + return freq / (post_div + 1) / 2; +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return get_root_clk(ARM_A7_CLK_ROOT); + case MXC_AXI_CLK: + return get_root_clk(MAIN_AXI_CLK_ROOT); + case MXC_AHB_CLK: + return get_root_clk(AHB_CLK_ROOT); + case MXC_IPG_CLK: + return get_ipg_clk(); + case MXC_I2C_CLK: + return get_root_clk(I2C1_CLK_ROOT); + case MXC_UART_CLK: + return get_root_clk(UART1_CLK_ROOT); + case MXC_CSPI_CLK: + return get_root_clk(ECSPI1_CLK_ROOT); + case MXC_DDR_CLK: + return get_ddrc_clk(); + case MXC_ESDHC_CLK: + return get_root_clk(USDHC1_CLK_ROOT); + case MXC_ESDHC2_CLK: + return get_root_clk(USDHC2_CLK_ROOT); + case MXC_ESDHC3_CLK: + return get_root_clk(USDHC3_CLK_ROOT); + default: + printf("Unsupported mxc_clock %d\n", clk); + break; + } + + return 0; +} + +#ifdef CONFIG_SYS_I2C_MXC +/* i2c_num can be 0 - 3 */ +int enable_i2c_clk(unsigned char enable, unsigned i2c_num) +{ + u32 target; + + if (i2c_num >= 4) + return -EINVAL; + + if (enable) { + clock_enable(CCGR_I2C1 + i2c_num, 0); + + /* Set i2c root clock to PLL_SYS_MAIN_120M_CLK */ + + target = CLK_ROOT_ON | I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); + clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target); + + clock_enable(CCGR_I2C1 + i2c_num, 1); + } else { + clock_enable(CCGR_I2C1 + i2c_num, 0); + } + + return 0; +} +#endif + +static void init_clk_esdhc(void) +{ + u32 target; + + /* disable the clock gate first */ + clock_enable(CCGR_USDHC1, 0); + clock_enable(CCGR_USDHC2, 0); + clock_enable(CCGR_USDHC3, 0); + + /* 196: 392/2 */ + target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); + clock_set_target_val(USDHC1_CLK_ROOT, target); + + target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); + clock_set_target_val(USDHC2_CLK_ROOT, target); + + target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); + clock_set_target_val(USDHC3_CLK_ROOT, target); + + /* enable the clock gate */ + clock_enable(CCGR_USDHC1, 1); + clock_enable(CCGR_USDHC2, 1); + clock_enable(CCGR_USDHC3, 1); + +} + +static void init_clk_uart(void) +{ + u32 target; + + /* disable the clock gate first */ + clock_enable(CCGR_UART1, 0); + clock_enable(CCGR_UART2, 0); + clock_enable(CCGR_UART3, 0); + clock_enable(CCGR_UART4, 0); + clock_enable(CCGR_UART5, 0); + clock_enable(CCGR_UART6, 0); + clock_enable(CCGR_UART7, 0); + + /* 24Mhz */ + target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(UART1_CLK_ROOT, target); + + target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(UART2_CLK_ROOT, target); + + target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(UART3_CLK_ROOT, target); + + target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(UART4_CLK_ROOT, target); + + target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(UART5_CLK_ROOT, target); + + target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(UART6_CLK_ROOT, target); + + target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(UART7_CLK_ROOT, target); + + /* enable the clock gate */ + clock_enable(CCGR_UART1, 1); + clock_enable(CCGR_UART2, 1); + clock_enable(CCGR_UART3, 1); + clock_enable(CCGR_UART4, 1); + clock_enable(CCGR_UART5, 1); + clock_enable(CCGR_UART6, 1); + clock_enable(CCGR_UART7, 1); + +} + +static void init_clk_weim(void) +{ + u32 target; + + /* disable the clock gate first */ + clock_enable(CCGR_WEIM, 0); + + /* 120Mhz */ + target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(EIM_CLK_ROOT, target); + + /* enable the clock gate */ + clock_enable(CCGR_WEIM, 1); +} + +static void init_clk_ecspi(void) +{ + u32 target; + + /* disable the clock gate first */ + clock_enable(CCGR_ECSPI1, 0); + clock_enable(CCGR_ECSPI2, 0); + clock_enable(CCGR_ECSPI3, 0); + clock_enable(CCGR_ECSPI4, 0); + + /* 60Mhz: 240/4 */ + target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); + clock_set_target_val(ECSPI1_CLK_ROOT, target); + + target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); + clock_set_target_val(ECSPI2_CLK_ROOT, target); + + target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); + clock_set_target_val(ECSPI3_CLK_ROOT, target); + + target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); + clock_set_target_val(ECSPI4_CLK_ROOT, target); + + /* enable the clock gate */ + clock_enable(CCGR_ECSPI1, 1); + clock_enable(CCGR_ECSPI2, 1); + clock_enable(CCGR_ECSPI3, 1); + clock_enable(CCGR_ECSPI4, 1); +} + +static void init_clk_wdog(void) +{ + u32 target; + + /* disable the clock gate first */ + clock_enable(CCGR_WDOG1, 0); + clock_enable(CCGR_WDOG2, 0); + clock_enable(CCGR_WDOG3, 0); + clock_enable(CCGR_WDOG4, 0); + + /* 24Mhz */ + target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(WDOG_CLK_ROOT, target); + + /* enable the clock gate */ + clock_enable(CCGR_WDOG1, 1); + clock_enable(CCGR_WDOG2, 1); + clock_enable(CCGR_WDOG3, 1); + clock_enable(CCGR_WDOG4, 1); + +} + +#ifdef CONFIG_MXC_EPDC +static void init_clk_epdc(void) +{ + u32 target; + + /* disable the clock gate first */ + clock_enable(CCGR_EPDC, 0); + + /* 24Mhz */ + target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV12); + clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target); + + /* enable the clock gate */ + clock_enable(CCGR_EPDC, 1); +} +#endif + +static int enable_pll_enet(void) +{ + u32 reg; + s32 timeout = 100000; + + reg = readl(&ccm_anatop->pll_enet); + /* If pll_enet powered up, no need to set it again */ + if (reg & ANADIG_PLL_ENET_PWDN_MASK) { + reg &= ~ANADIG_PLL_ENET_PWDN_MASK; + writel(reg, &ccm_anatop->pll_enet); + + while (timeout--) { + if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK) + break; + } + + if (timeout <= 0) { + /* If timeout, we set pwdn for pll_enet. */ + reg |= ANADIG_PLL_ENET_PWDN_MASK; + return -ETIME; + } + } + + /* Clear bypass */ + writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr); + + writel((CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK + | CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK + | CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK + | CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK + | CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK + | CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK + | CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK), + &ccm_anatop->pll_enet_set); + + return 0; +} +static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom, + u32 post_div) +{ + u32 reg = 0; + ulong start; + + debug("pll5 div = %d, num = %d, denom = %d\n", + pll_div, pll_num, pll_denom); + + /* Power up PLL5 video and disable its output */ + writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK | + CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK | + CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK | + CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK | + CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK | + CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK, + &ccm_anatop->pll_video_clr); + + /* Set div, num and denom */ + switch (post_div) { + case 1: + writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | + CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x1) | + CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0), + &ccm_anatop->pll_video_set); + break; + case 2: + writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | + CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) | + CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0), + &ccm_anatop->pll_video_set); + break; + case 3: + writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | + CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) | + CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x1), + &ccm_anatop->pll_video_set); + break; + case 4: + writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | + CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) | + CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x3), + &ccm_anatop->pll_video_set); + break; + case 0: + default: + writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | + CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x2) | + CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0), + &ccm_anatop->pll_video_set); + break; + } + + writel(CCM_ANALOG_PLL_VIDEO_NUM_A(pll_num), + &ccm_anatop->pll_video_num); + + writel(CCM_ANALOG_PLL_VIDEO_DENOM_B(pll_denom), + &ccm_anatop->pll_video_denom); + + /* Wait PLL5 lock */ + start = get_timer(0); /* Get current timestamp */ + + do { + reg = readl(&ccm_anatop->pll_video); + if (reg & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) { + /* Enable PLL out */ + writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK, + &ccm_anatop->pll_video_set); + return 0; + } + } while (get_timer(0) < (start + 10)); /* Wait 10ms */ + + printf("Lock PLL5 timeout\n"); + + return 1; + +} + +int set_clk_qspi(void) +{ + u32 target; + + /* disable the clock gate first */ + clock_enable(CCGR_QSPI, 0); + + /* 49M: 392/2/4 */ + target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); + clock_set_target_val(QSPI_CLK_ROOT, target); + + /* enable the clock gate */ + clock_enable(CCGR_QSPI, 1); + + return 0; +} + +int set_clk_nand(void) +{ + u32 target; + + /* disable the clock gate first */ + clock_enable(CCGR_RAWNAND, 0); + + enable_pll_enet(); + /* 100: 500/5 */ + target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV5); + clock_set_target_val(NAND_CLK_ROOT, target); + + /* enable the clock gate */ + clock_enable(CCGR_RAWNAND, 1); + + return 0; +} + +void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq) +{ + u32 hck = MXC_HCLK/1000; + u32 min = hck * 27; + u32 max = hck * 54; + u32 temp, best = 0; + u32 i, j, pred = 1, postd = 1; + u32 pll_div, pll_num, pll_denom, post_div = 0; + u32 target; + + debug("mxs_set_lcdclk, freq = %d\n", freq); + + clock_enable(CCGR_LCDIF, 0); + + temp = (freq * 8 * 8); + if (temp < min) { + + for (i = 1; i <= 4; i++) { + if ((temp * (1 << i)) > min) { + post_div = i; + freq = (freq * (1 << i)); + break; + } + } + + if (5 == i) { + printf("Fail to set rate to %dkhz", freq); + return; + } + } + + for (i = 1; i <= 8; i++) { + for (j = 1; j <= 8; j++) { + temp = freq * i * j; + if (temp > max || temp < min) + continue; + + if (best == 0 || temp < best) { + best = temp; + pred = i; + postd = j; + } + } + } + + if (best == 0) { + printf("Fail to set rate to %dkhz", freq); + return; + } + + debug("best %d, pred = %d, postd = %d\n", best, pred, postd); + + pll_div = best / hck; + pll_denom = 1000000; + pll_num = (best - hck * pll_div) * pll_denom / hck; + + if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) + return; + + target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK | + CLK_ROOT_PRE_DIV((pred - 1)) | CLK_ROOT_POST_DIV((postd - 1)); + clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target); + + clock_enable(CCGR_LCDIF, 1); +} + +#ifdef CONFIG_FEC_MXC +int set_clk_enet(enum enet_freq type) +{ + u32 target; + int ret; + u32 enet1_ref, enet2_ref; + + /* disable the clock first */ + clock_enable(CCGR_ENET1, 0); + clock_enable(CCGR_ENET2, 0); + + switch (type) { + case ENET_125MHz: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; + enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; + break; + case ENET_50MHz: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; + enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; + break; + case ENET_25MHz: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; + enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; + break; + default: + return -EINVAL; + } + + ret = enable_pll_enet(); + if (ret != 0) + return ret; + + /* set enet axi clock 196M: 392/2 */ + target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); + clock_set_target_val(ENET_AXI_CLK_ROOT, target); + + target = CLK_ROOT_ON | enet1_ref | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(ENET1_REF_CLK_ROOT, target); + + target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); + clock_set_target_val(ENET1_TIME_CLK_ROOT, target); + + target = CLK_ROOT_ON | enet2_ref | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(ENET2_REF_CLK_ROOT, target); + + target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); + clock_set_target_val(ENET2_TIME_CLK_ROOT, target); + +#ifdef CONFIG_FEC_MXC_25M_REF_CLK + target = CLK_ROOT_ON | ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target); +#endif + /* enable clock */ + clock_enable(CCGR_ENET1, 1); + clock_enable(CCGR_ENET2, 1); + + return 0; +} +#endif + +/* Configure PLL/PFD freq */ +void clock_init(void) +{ + /* Rom has enabled PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET + * In u-boot, we have to: + * 1. Configure PFD3- PFD7 for freq we needed in u-boot + * 2. Set clock root for peripherals (ip channel) used in u-boot but without set rate + * interface. The clocks for these peripherals are enabled after this intialization. + * 3. Other peripherals with set clock rate interface does not be set in this function. + */ + + u32 reg; + + /* + * Configure PFD4 to 392M + * 480M * 18 / 0x16 = 392M + */ + reg = readl(&ccm_anatop->pfd_480b); + + reg &= ~(ANATOP_PFD480B_PFD4_FRAC_MASK | + CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK); + reg |= ANATOP_PFD480B_PFD4_FRAC_392M_VAL; + + writel(reg, &ccm_anatop->pfd_480b); + + init_clk_esdhc(); + init_clk_uart(); + init_clk_weim(); + init_clk_ecspi(); + init_clk_wdog(); +#ifdef CONFIG_MXC_EPDC + init_clk_epdc(); +#endif + + enable_usboh3_clk(1); + + clock_enable(CCGR_SNVS, 1); + +#ifdef CONFIG_NAND_MXS + clock_enable(CCGR_RAWNAND, 1); +#endif +} + +#ifdef CONFIG_SECURE_BOOT +void hab_caam_clock_enable(unsigned char enable) +{ + if (enable) + clock_enable(CCGR_CAAM, 1); + else + clock_enable(CCGR_CAAM, 0); +} +#endif + +#ifdef CONFIG_MXC_EPDC +void epdc_clock_enable(void) +{ + clock_enable(CCGR_EPDC, 1); +} +void epdc_clock_disable(void) +{ + clock_enable(CCGR_EPDC, 0); +} +#endif + +/* + * Dump some core clockes. + */ +int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + u32 freq; + freq = decode_pll(PLL_CORE, MXC_HCLK); + printf("PLL_CORE %8d MHz\n", freq / 1000000); + freq = decode_pll(PLL_SYS, MXC_HCLK); + printf("PLL_SYS %8d MHz\n", freq / 1000000); + freq = decode_pll(PLL_ENET, MXC_HCLK); + printf("PLL_NET %8d MHz\n", freq / 1000000); + + printf("\n"); + + printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); + printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); +#ifdef CONFIG_MXC_SPI + printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); +#endif + printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); + printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); + printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); + printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); + printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); + printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); + + return 0; +} + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks, + "display clocks", + "" +); diff --git a/arch/arm/cpu/armv7/mx7/clock_slice.c b/arch/arm/cpu/armv7/mx7/clock_slice.c new file mode 100644 index 0000000..ad5d504 --- /dev/null +++ b/arch/arm/cpu/armv7/mx7/clock_slice.c @@ -0,0 +1,757 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Author: + * Peng Fan Peng.Fan@freescale.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <div64.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> + +struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + +static struct clk_root_map root_array[] = { + {ARM_A7_CLK_ROOT, CCM_CORE_CHANNEL, + {OSC_24M_CLK, PLL_ARM_MAIN_800M_CLK, PLL_ENET_MAIN_500M_CLK, + PLL_DRAM_MAIN_1066M_CLK, PLL_SYS_MAIN_480M_CLK, + PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_USB_MAIN_480M_CLK} + }, + {ARM_M4_CLK_ROOT, CCM_BUS_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_250M_CLK, + PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, + PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK} + }, + {ARM_M0_CLK_ROOT, CCM_BUS_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_125M_CLK, + PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, + PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK} + }, + {MAIN_AXI_CLK_ROOT, CCM_BUS_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK, + PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD5_CLK, PLL_AUDIO_MAIN_CLK, + PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD7_CLK} + }, + {DISP_AXI_CLK_ROOT, CCM_BUS_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK, + PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK, + PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK} + }, + {ENET_AXI_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK, + PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_AUDIO_MAIN_CLK, + PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK} + }, + {NAND_USDHC_BUS_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK, + PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_PFD6_CLK, + PLL_ENET_MAIN_250M_CLK, PLL_AUDIO_MAIN_CLK} + }, + {AHB_CLK_ROOT, CCM_AHB_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK, + PLL_SYS_PFD0_392M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK, + PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK} + }, + {DRAM_PHYM_CLK_ROOT, CCM_DRAM_PHYM_CHANNEL, + {PLL_DRAM_MAIN_1066M_CLK, DRAM_PHYM_ALT_CLK_ROOT} + }, + {DRAM_CLK_ROOT, CCM_DRAM_CHANNEL, + {PLL_DRAM_MAIN_1066M_CLK, DRAM_ALT_CLK_ROOT} + }, + {DRAM_PHYM_ALT_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK, + PLL_ENET_MAIN_500M_CLK, PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD7_CLK, + PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK} + }, + {DRAM_ALT_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK, + PLL_ENET_MAIN_500M_CLK, PLL_ENET_MAIN_250M_CLK, + PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_SYS_PFD2_270M_CLK} + }, + {USB_HSIC_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_USB_MAIN_480M_CLK, + PLL_SYS_PFD3_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD5_CLK, + PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK} + }, + {PCIE_CTRL_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK, + PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK, + PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_SYS_PFD6_CLK} + }, + {PCIE_PHY_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_ENET_MAIN_500M_CLK, + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, + EXT_CLK_4, PLL_SYS_PFD0_392M_CLK} + }, + {EPDC_PIXEL_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK, + PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD6_CLK, + PLL_SYS_PFD7_CLK, PLL_VIDEO_MAIN_CLK} + }, + {LCDIF_PIXEL_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_DRAM_MAIN_533M_CLK, + EXT_CLK_3, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK, + PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK} + }, + {MIPI_DSI_EXTSER_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD3_CLK, + PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK, + PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK} + }, + {MIPI_CSI_WARP_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD3_CLK, + PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK, + PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK} + }, + {MIPI_DPHY_REF_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK, + PLL_SYS_PFD5_CLK, REF_1M_CLK, EXT_CLK_2, + PLL_VIDEO_MAIN_CLK, EXT_CLK_3} + }, + {SAI1_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK, + PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK, + PLL_ENET_MAIN_125M_CLK, EXT_CLK_2} + }, + {SAI2_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK, + PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK, + PLL_ENET_MAIN_125M_CLK, EXT_CLK_2} + }, + {SAI3_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK, + PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK, + PLL_ENET_MAIN_125M_CLK, EXT_CLK_3} + }, + {SPDIF_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK, + PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK, + PLL_ENET_MAIN_125M_CLK, EXT_CLK_3} + }, + {ENET1_REF_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK, + PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK, + PLL_VIDEO_MAIN_CLK, EXT_CLK_4} + }, + {ENET1_TIME_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK, + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, + EXT_CLK_4, PLL_VIDEO_MAIN_CLK} + }, + {ENET2_REF_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK, + PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK, + PLL_VIDEO_MAIN_CLK, EXT_CLK_4} + }, + {ENET2_TIME_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK, + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, + EXT_CLK_4, PLL_VIDEO_MAIN_CLK} + }, + {ENET_PHY_REF_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_ENET_MAIN_25M_CLK, PLL_ENET_MAIN_50M_CLK, + PLL_ENET_MAIN_125M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, + PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD3_CLK} + }, + {EIM_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK, + PLL_DRAM_MAIN_533M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_SYS_PFD3_CLK, + PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK} + }, + {NAND_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_DRAM_MAIN_533M_CLK, + PLL_SYS_PFD0_392M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK, + PLL_ENET_MAIN_250M_CLK, PLL_VIDEO_MAIN_CLK} + }, + {QSPI_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_DRAM_MAIN_533M_CLK, + PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD3_CLK, PLL_SYS_PFD2_270M_CLK, + PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK} + }, + {USDHC1_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK, + PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK, + PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK} + }, + {USDHC2_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK, + PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK, + PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK} + }, + {USDHC3_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK, + PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK, + PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK} + }, + {CAN1_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK, + PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK, + EXT_CLK_1, EXT_CLK_4} + }, + {CAN2_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK, + PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK, + EXT_CLK_1, EXT_CLK_3} + }, + {I2C1_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK, + PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK, + PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK} + }, + {I2C2_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK, + PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK, + PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK} + }, + {I2C3_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK, + PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK, + PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK} + }, + {I2C4_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK, + PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK, + PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK} + }, + {UART1_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK, + PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2, + EXT_CLK_4, PLL_USB_MAIN_480M_CLK} + }, + {UART2_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK, + PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2, + EXT_CLK_3, PLL_USB_MAIN_480M_CLK} + }, + {UART3_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK, + PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2, + EXT_CLK_4, PLL_USB_MAIN_480M_CLK} + }, + {UART4_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK, + PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2, + EXT_CLK_3, PLL_USB_MAIN_480M_CLK} + }, + {UART5_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK, + PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2, + EXT_CLK_4, PLL_USB_MAIN_480M_CLK} + }, + {UART6_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK, + PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2, + EXT_CLK_3, PLL_USB_MAIN_480M_CLK} + }, + {UART7_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK, + PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2, + EXT_CLK_4, PLL_USB_MAIN_480M_CLK} + }, + {ECSPI1_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK, + PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK, + PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK} + }, + {ECSPI2_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK, + PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK, + PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK} + }, + {ECSPI3_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK, + PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK, + PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK} + }, + {ECSPI4_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK, + PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK, + PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK} + }, + {PWM1_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK, + PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1, + REF_1M_CLK, PLL_VIDEO_MAIN_CLK} + }, + {PWM2_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK, + PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1, + REF_1M_CLK, PLL_VIDEO_MAIN_CLK} + }, + {PWM3_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK, + PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2, + REF_1M_CLK, PLL_VIDEO_MAIN_CLK} + }, + {PWM4_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK, + PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2, + REF_1M_CLK, PLL_VIDEO_MAIN_CLK} + }, + {FLEXTIMER1_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK, + PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3, + REF_1M_CLK, PLL_VIDEO_MAIN_CLK} + }, + {FLEXTIMER2_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK, + PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3, + REF_1M_CLK, PLL_VIDEO_MAIN_CLK} + }, + {SIM1_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK, + PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_AUDIO_MAIN_CLK, + PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK} + }, + {SIM2_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK, + PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_VIDEO_MAIN_CLK, + PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK} + }, + {GPT1_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK, + PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK, + PLL_AUDIO_MAIN_CLK, EXT_CLK_1} + }, + {GPT2_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK, + PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK, + PLL_AUDIO_MAIN_CLK, EXT_CLK_2} + }, + {GPT3_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK, + PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK, + PLL_AUDIO_MAIN_CLK, EXT_CLK_3} + }, + {GPT4_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK, + PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK, + PLL_AUDIO_MAIN_CLK, EXT_CLK_4} + }, + {TRACE_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK, + PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK, + EXT_CLK_1, EXT_CLK_3} + }, + {WDOG_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK, + PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK, + REF_1M_CLK, PLL_SYS_PFD1_166M_CLK} + }, + {CSI_MCLK_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK, + PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK, + PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK} + }, + {AUDIO_MCLK_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK, + PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK, + PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK} + }, + {WRCLK_CLK_ROOT, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_DRAM_MAIN_533M_CLK, + PLL_USB_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_270M_CLK, + PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD7_CLK} + }, + {IPP_DO_CLKO1, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK, + PLL_SYS_PFD0_196M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK, + PLL_DRAM_MAIN_533M_CLK, REF_1M_CLK} + }, + {IPP_DO_CLKO2, CCM_IP_CHANNEL, + {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD0_392M_CLK, + PLL_SYS_PFD1_166M_CLK, PLL_SYS_PFD4_CLK, PLL_AUDIO_MAIN_CLK, + PLL_VIDEO_MAIN_CLK, OSC_32K_CLK} + }, +}; + +/* select which entry of root_array */ +static int select(enum clk_root_index clock_id) +{ + int i, size; + struct clk_root_map *p = root_array; + + size = ARRAY_SIZE(root_array); + + for (i = 0; i < size; i++, p++) { + if (clock_id == p->entry) + return i; + } + + return -EINVAL; +} + +static int src_supported(int entry, enum clk_root_src clock_src) +{ + int i, size; + struct clk_root_map *p = &root_array[entry]; + + if ((p->type == CCM_DRAM_PHYM_CHANNEL) || (p->type == CCM_DRAM_CHANNEL)) + size = 2; + else + size = 8; + + for (i = 0; i < size; i++) { + if (p->src_mux[i] == clock_src) + return i; + } + + return -EINVAL; +} + +/* Set src for clock root slice. */ +int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src) +{ + int root_entry, src_entry; + u32 reg; + + if (clock_id >= CLK_ROOT_MAX) + return -EINVAL; + + root_entry = select(clock_id); + if (root_entry < 0) + return -EINVAL; + + src_entry = src_supported(root_entry, clock_src); + if (src_entry < 0) + return -EINVAL; + + reg = __raw_readl(&imx_ccm->root[clock_id].target_root); + reg &= ~CLK_ROOT_MUX_MASK; + reg |= src_entry << CLK_ROOT_MUX_SHIFT; + __raw_writel(reg, &imx_ccm->root[clock_id].target_root); + + return 0; +} + +/* Get src of a clock root slice. */ +int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src) +{ + u32 val; + int root_entry; + struct clk_root_map *p; + + if (clock_id >= CLK_ROOT_MAX) + return -EINVAL; + + val = __raw_readl(&imx_ccm->root[clock_id].target_root); + val &= CLK_ROOT_MUX_MASK; + val >>= CLK_ROOT_MUX_SHIFT; + + root_entry = select(clock_id); + if (root_entry < 0) + return -EINVAL; + + p = &root_array[root_entry]; + *p_clock_src = p->src_mux[val]; + + return 0; +} + +int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div) +{ + int root_entry; + struct clk_root_map *p; + u32 reg; + + if (clock_id >= CLK_ROOT_MAX) + return -EINVAL; + + root_entry = select(clock_id); + if (root_entry < 0) + return -EINVAL; + + p = &root_array[root_entry]; + + if ((p->type == CCM_CORE_CHANNEL) || + (p->type == CCM_DRAM_PHYM_CHANNEL) || + (p->type == CCM_DRAM_CHANNEL)) { + if (pre_div != CLK_ROOT_PRE_DIV1) { + printf("Error pre div!\n"); + return -EINVAL; + } + } + + reg = __raw_readl(&imx_ccm->root[clock_id].target_root); + reg &= ~CLK_ROOT_PRE_DIV_MASK; + reg |= pre_div << CLK_ROOT_PRE_DIV_SHIFT; + __raw_writel(reg, &imx_ccm->root[clock_id].target_root); + + return 0; +} + +int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div) +{ + u32 val; + int root_entry; + struct clk_root_map *p; + + if (clock_id >= CLK_ROOT_MAX) + return -EINVAL; + + root_entry = select(clock_id); + if (root_entry < 0) + return -EINVAL; + + p = &root_array[root_entry]; + + if ((p->type == CCM_CORE_CHANNEL) || + (p->type == CCM_DRAM_PHYM_CHANNEL) || + (p->type == CCM_DRAM_CHANNEL)) { + *pre_div = 0; + return 0; + } + + val = __raw_readl(&imx_ccm->root[clock_id].target_root); + val &= CLK_ROOT_PRE_DIV_MASK; + val >>= CLK_ROOT_PRE_DIV_SHIFT; + + *pre_div = val; + + return 0; +} + +int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div) +{ + u32 reg; + + if (clock_id >= CLK_ROOT_MAX) + return -EINVAL; + + if (clock_id == DRAM_PHYM_CLK_ROOT) { + if (div != CLK_ROOT_POST_DIV1) { + printf("Error post div!\n"); + return -EINVAL; + } + } + + /* Only 3 bit post div. */ + if ((clock_id == DRAM_CLK_ROOT) && (div > CLK_ROOT_POST_DIV7)) { + printf("Error post div!\n"); + return -EINVAL; + } + + reg = __raw_readl(&imx_ccm->root[clock_id].target_root); + reg &= ~CLK_ROOT_POST_DIV_MASK; + reg |= div << CLK_ROOT_POST_DIV_SHIFT; + __raw_writel(reg, &imx_ccm->root[clock_id].target_root); + + return 0; +} + +int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div) +{ + u32 val; + + if (clock_id >= CLK_ROOT_MAX) + return -EINVAL; + + if (clock_id == DRAM_PHYM_CLK_ROOT) { + *div = 0; + return 0; + } + + val = __raw_readl(&imx_ccm->root[clock_id].target_root); + if (clock_id == DRAM_CLK_ROOT) + val &= DRAM_CLK_ROOT_POST_DIV_MASK; + else + val &= CLK_ROOT_POST_DIV_MASK; + val >>= CLK_ROOT_POST_DIV_SHIFT; + + *div = val; + + return 0; +} + +int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div, + int auto_en) +{ + u32 val; + int root_entry; + struct clk_root_map *p; + + if (clock_id >= CLK_ROOT_MAX) + return -EINVAL; + + root_entry = select(clock_id); + if (root_entry < 0) + return -EINVAL; + + p = &root_array[root_entry]; + + if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) { + printf("Auto postdiv not supported.!\n"); + return -EINVAL; + } + + /* + * Each time only one filed can be changed, no use target_root_set. + */ + val = __raw_readl(&imx_ccm->root[clock_id].target_root); + val &= ~CLK_ROOT_AUTO_DIV_MASK; + val |= (div << CLK_ROOT_AUTO_DIV_SHIFT); + + if (auto_en) + val |= CLK_ROOT_AUTO_EN; + else + val &= ~CLK_ROOT_AUTO_EN; + + __raw_writel(val, &imx_ccm->root[clock_id].target_root); + + return 0; +} + +int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div, + int *auto_en) +{ + u32 val; + int root_entry; + struct clk_root_map *p; + + if (clock_id >= CLK_ROOT_MAX) + return -EINVAL; + + root_entry = select(clock_id); + if (root_entry < 0) + return -EINVAL; + + p = &root_array[root_entry]; + + /* + * Only bus/ahb channel supports auto div. + * If unsupported, just set auto_en and div with 0. + */ + if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) { + *auto_en = 0; + *div = 0; + return 0; + } + + val = __raw_readl(&imx_ccm->root[clock_id].target_root); + if ((val & CLK_ROOT_AUTO_EN_MASK) == 0) + *auto_en = 0; + else + *auto_en = 1; + + val &= CLK_ROOT_AUTO_DIV_MASK; + val >>= CLK_ROOT_AUTO_DIV_SHIFT; + + *div = val; + + return 0; +} + +int clock_get_target_val(enum clk_root_index clock_id, u32 *val) +{ + if (clock_id >= CLK_ROOT_MAX) + return -EINVAL; + + *val = __raw_readl(&imx_ccm->root[clock_id].target_root); + + return 0; +} + +int clock_set_target_val(enum clk_root_index clock_id, u32 val) +{ + if (clock_id >= CLK_ROOT_MAX) + return -EINVAL; + + __raw_writel(val, &imx_ccm->root[clock_id].target_root); + + return 0; +} + +/* Auto_div and auto_en is ignored, they are rarely used. */ +int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div, + enum root_post_div post_div, enum clk_root_src clock_src) +{ + u32 val; + int root_entry, src_entry; + struct clk_root_map *p; + + if (clock_id >= CLK_ROOT_MAX) + return -EINVAL; + + root_entry = select(clock_id); + if (root_entry < 0) + return -EINVAL; + + p = &root_array[root_entry]; + + if ((p->type == CCM_CORE_CHANNEL) || + (p->type == CCM_DRAM_PHYM_CHANNEL) || + (p->type == CCM_DRAM_CHANNEL)) { + if (pre_div != CLK_ROOT_PRE_DIV1) { + printf("Error pre div!\n"); + return -EINVAL; + } + } + + /* Only 3 bit post div. */ + if (p->type == CCM_DRAM_CHANNEL) { + if (post_div > CLK_ROOT_POST_DIV7) { + printf("Error post div!\n"); + return -EINVAL; + } + } + + if (p->type == CCM_DRAM_PHYM_CHANNEL) { + if (post_div != CLK_ROOT_POST_DIV1) { + printf("Error post div!\n"); + return -EINVAL; + } + } + + src_entry = src_supported(root_entry, clock_src); + if (src_entry < 0) + return -EINVAL; + + val = CLK_ROOT_ON | pre_div << CLK_ROOT_PRE_DIV_SHIFT | + post_div << CLK_ROOT_POST_DIV_SHIFT | + src_entry << CLK_ROOT_MUX_SHIFT; + + __raw_writel(val, &imx_ccm->root[clock_id].target_root); + + return 0; +} + +int clock_root_enabled(enum clk_root_index clock_id) +{ + u32 val; + + if (clock_id >= CLK_ROOT_MAX) + return -EINVAL; + + /* + * No enable bit for DRAM controller and PHY. Just return enabled. + */ + if ((clock_id == DRAM_PHYM_CLK_ROOT) || (clock_id == DRAM_CLK_ROOT)) + return 1; + + val = __raw_readl(&imx_ccm->root[clock_id].target_root); + + return (val & CLK_ROOT_ENABLE_MASK) ? 1 : 0; +} + +/* CCGR gate operation */ +int clock_enable(enum clk_ccgr_index index, bool enable) +{ + if (index >= CCGR_MAX) + return -EINVAL; + + if (enable) + __raw_writel(CCM_CLK_ON_MSK, + &imx_ccm->ccgr_array[index].ccgr_set); + else + __raw_writel(CCM_CLK_ON_MSK, + &imx_ccm->ccgr_array[index].ccgr_clr); + + return 0; +} diff --git a/arch/arm/cpu/armv7/mx7/hab.c b/arch/arm/cpu/armv7/mx7/hab.c new file mode 100644 index 0000000..43b06bd --- /dev/null +++ b/arch/arm/cpu/armv7/mx7/hab.c @@ -0,0 +1,277 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hab.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> + +/* -------- start of HAB API updates ------------*/ +#define hab_rvt_report_event_p \ +( \ + ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \ +) + +#define hab_rvt_report_status_p \ +( \ + ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \ +) + +#define hab_rvt_authenticate_image_p \ +( \ + ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \ +) + +#define hab_rvt_entry_p \ +( \ + ((hab_rvt_entry_t *)HAB_RVT_ENTRY) \ +) + +#define hab_rvt_exit_p \ +( \ + ((hab_rvt_exit_t *)HAB_RVT_EXIT) \ +) + +#define IVT_SIZE 0x20 +#define ALIGN_SIZE 0x1000 +#define CSF_PAD_SIZE 0x2000 + +/* + * +------------+ 0x0 (DDR_UIMAGE_START) - + * | Header | | + * +------------+ 0x40 | + * | | | + * | | | + * | | | + * | | | + * | Image Data | | + * . | | + * . | > Stuff to be authenticated ----+ + * . | | | + * | | | | + * | | | | + * +------------+ | | + * | | | | + * | Fill Data | | | + * | | | | + * +------------+ Align to ALIGN_SIZE | | + * | IVT | | | + * +------------+ + IVT_SIZE - | + * | | | + * | CSF DATA | <---------------------------------------------------------+ + * | | + * +------------+ + * | | + * | Fill Data | + * | | + * +------------+ + CSF_PAD_SIZE + */ + +bool is_hab_enabled(void) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[1]; + struct fuse_bank1_regs *fuse = + (struct fuse_bank1_regs *)bank->fuse_regs; + uint32_t reg = readl(&fuse->cfg0); + + return (reg & 0x2000000) == 0x2000000; +} + +void display_event(uint8_t *event_data, size_t bytes) +{ + uint32_t i; + + if (!(event_data && bytes > 0)) + return; + + for (i = 0; i < bytes; i++) { + if (i == 0) + printf("\t0x%02x", event_data[i]); + else if ((i % 8) == 0) + printf("\n\t0x%02x", event_data[i]); + else + printf(" 0x%02x", event_data[i]); + } +} + +int get_hab_status(void) +{ + uint32_t index = 0; /* Loop index */ + uint8_t event_data[128]; /* Event data buffer */ + size_t bytes = sizeof(event_data); /* Event size in bytes */ + enum hab_config config = 0; + enum hab_state state = 0; + hab_rvt_report_event_t *hab_rvt_report_event; + hab_rvt_report_status_t *hab_rvt_report_status; + + if (is_hab_enabled()) + puts("\nSecure boot enabled\n"); + else + puts("\nSecure boot disabled\n"); + + hab_rvt_report_event = hab_rvt_report_event_p; + hab_rvt_report_status = hab_rvt_report_status_p; + + /* Check HAB status */ + if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) { + printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n", + config, state); + + /* Display HAB Error events */ + while (hab_rvt_report_event(HAB_FAILURE, index, event_data, + &bytes) == HAB_SUCCESS) { + puts("\n"); + printf("--------- HAB Event %d -----------------\n", + index + 1); + puts("event data:\n"); + display_event(event_data, bytes); + puts("\n"); + bytes = sizeof(event_data); + index++; + } + } + /* Display message if no HAB events are found */ + else { + printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n", + config, state); + puts("No HAB Events Found!\n\n"); + } + return 0; +} + +#ifdef DEBUG_AUTHENTICATE_IMAGE +void dump_mem(uint32_t addr, int size) +{ + int i; + + for (i = 0; i < size; i += 4) { + if (i != 0) { + if (i % 16 == 0) + printf("\n"); + else + printf(" "); + } + + printf("0x%08x", *(uint32_t *)addr); + addr += 4; + } + + printf("\n"); + + return; +} +#endif + +uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size) +{ + uint32_t load_addr = 0; + size_t bytes; + ptrdiff_t ivt_offset = 0; + int result = 0; + ulong start; + hab_rvt_authenticate_image_t *hab_rvt_authenticate_image; + hab_rvt_entry_t *hab_rvt_entry; + hab_rvt_exit_t *hab_rvt_exit; + + hab_rvt_authenticate_image = hab_rvt_authenticate_image_p; + hab_rvt_entry = hab_rvt_entry_p; + hab_rvt_exit = hab_rvt_exit_p; + + if (is_hab_enabled()) { + printf("\nAuthenticate uImage from DDR location 0x%x...\n", + ddr_start); + + hab_caam_clock_enable(1); + + if (hab_rvt_entry() == HAB_SUCCESS) { + /* If not already aligned, Align to ALIGN_SIZE */ + ivt_offset = (image_size + ALIGN_SIZE - 1) & + ~(ALIGN_SIZE - 1); + + start = ddr_start; + bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE; + +#ifdef DEBUG_AUTHENTICATE_IMAGE + printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n", + ivt_offset, ddr_start + ivt_offset); + printf("Dumping IVT\n"); + dump_mem(ddr_start + ivt_offset, 0x20); + + printf("Dumping CSF Header\n"); + dump_mem(ddr_start + ivt_offset + 0x20, 0x40); + + get_hab_status(); + + printf("\nCalling authenticate_image in ROM\n"); + printf("\tivt_offset = 0x%x\n\tstart = 0x%08x" + "\n\tbytes = 0x%x\n", ivt_offset, start, bytes); +#endif + load_addr = (uint32_t)hab_rvt_authenticate_image( + HAB_CID_UBOOT, + ivt_offset, (void **)&start, + (size_t *)&bytes, NULL); + if (hab_rvt_exit() != HAB_SUCCESS) { + printf("hab exit function fail\n"); + load_addr = 0; + } + } else + printf("hab entry function fail\n"); + + hab_caam_clock_enable(0); + + get_hab_status(); + } + + if ((!is_hab_enabled()) || (load_addr != 0)) + result = 1; + + return result; +} + +int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if ((argc != 1)) { + cmd_usage(cmdtp); + return 1; + } + + get_hab_status(); + + return 0; +} + +static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + ulong addr, ivt_offset; + int rcode = 0; + + if (argc < 3) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[1], NULL, 16); + ivt_offset = simple_strtoul(argv[2], NULL, 16); + + rcode = authenticate_image(addr, ivt_offset); + + return rcode; +} + +U_BOOT_CMD( + hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status, + "display HAB status", + "" + ); + +U_BOOT_CMD( + hab_auth_img, 3, 1, do_authenticate_image, + "authenticate image via HAB", + "addr ivt_offset\n" + "addr - image hex address\n" + "ivt_offset - hex offset of IVT in the image" + ); diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c new file mode 100644 index 0000000..88a1441 --- /dev/null +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -0,0 +1,409 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/armv7.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/dma.h> +#include <stdbool.h> +#include <asm/arch/crm_regs.h> +#include <dm.h> +#include <imx_thermal.h> +#ifdef CONFIG_VIDEO_MXS +#include <mxsfb.h> +#endif + +struct src *src_reg = (struct src *)SRC_BASE_ADDR; + +#if defined(CONFIG_IMX_THERMAL) +static const struct imx_thermal_plat imx7_thermal_plat = { + .regs = (void *)ANATOP_BASE_ADDR, + .fuse_bank = 3, + .fuse_word = 3, +}; + +U_BOOT_DEVICE(imx7_thermal) = { + .name = "imx_thermal", + .platdata = &imx7_thermal_plat, +}; +#endif + +u32 get_cpu_rev(void) +{ + struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) + ANATOP_BASE_ADDR; + u32 reg = readl(&ccm_anatop->digprog); + u32 type = (reg >> 16) & 0xff; + + reg &= 0xff; + return (type << 12) | reg; +} + +#ifdef CONFIG_REVISION_TAG +u32 __weak get_board_rev(void) +{ + u32 cpurev = get_cpu_rev(); + u32 type = ((cpurev >> 12) & 0xff); + + if (type == MXC_CPU_MX7D) + cpurev = (MXC_CPU_MX7D) << 12 | (cpurev & 0xFFF); + + return cpurev; +} +#endif + +static void init_aips(void) +{ + struct aipstz_regs *aips1, *aips2, *aips3; + + aips1 = (struct aipstz_regs *)AIPS1_ON_BASE_ADDR; + aips2 = (struct aipstz_regs *)AIPS2_ON_BASE_ADDR; + aips3 = (struct aipstz_regs *)AIPS3_ON_BASE_ADDR; + + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, &aips1->mprot0); + writel(0x77777777, &aips1->mprot1); + writel(0x77777777, &aips2->mprot0); + writel(0x77777777, &aips2->mprot1); + writel(0x77777777, &aips3->mprot0); + writel(0x77777777, &aips3->mprot1); + + /* + * Set all OPACRx to be non-bufferable, not require + * supervisor privilege level for access,allow for + * write access and untrusted master access. + */ + writel(0x00000000, &aips1->opacr0); + writel(0x00000000, &aips1->opacr1); + writel(0x00000000, &aips1->opacr2); + writel(0x00000000, &aips1->opacr3); + writel(0x00000000, &aips1->opacr4); + writel(0x00000000, &aips2->opacr0); + writel(0x00000000, &aips2->opacr1); + writel(0x00000000, &aips2->opacr2); + writel(0x00000000, &aips2->opacr3); + writel(0x00000000, &aips2->opacr4); + writel(0x00000000, &aips3->opacr0); + writel(0x00000000, &aips3->opacr1); + writel(0x00000000, &aips3->opacr2); + writel(0x00000000, &aips3->opacr3); + writel(0x00000000, &aips3->opacr4); +} + +static void imx_set_pcie_phy_power_down(void) +{ + /* TODO */ +} + +static void imx_set_wdog_powerdown(bool enable) +{ + struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; + struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; + struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; + struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR; + + writew(enable, &wdog1->wmcr); + writew(enable, &wdog2->wmcr); + writew(enable, &wdog3->wmcr); + writew(enable, &wdog4->wmcr); +} + +static void set_epdc_qos(void) +{ +#define REGS_QOS_BASE QOSC_IPS_BASE_ADDR +#define REGS_QOS_EPDC (QOSC_IPS_BASE_ADDR + 0x3400) +#define REGS_QOS_PXP0 (QOSC_IPS_BASE_ADDR + 0x2C00) +#define REGS_QOS_PXP1 (QOSC_IPS_BASE_ADDR + 0x3C00) + + writel(0, REGS_QOS_BASE); /* Disable clkgate & soft_reset */ + writel(0, REGS_QOS_BASE + 0x60); /* Enable all masters */ + writel(0, REGS_QOS_EPDC); /* Disable clkgate & soft_reset */ + writel(0, REGS_QOS_PXP0); /* Disable clkgate & soft_reset */ + writel(0, REGS_QOS_PXP1); /* Disable clkgate & soft_reset */ + + writel(0x0f020722, REGS_QOS_EPDC + 0xd0); /* WR, init = 7 with red flag */ + writel(0x0f020722, REGS_QOS_EPDC + 0xe0); /* RD, init = 7 with red flag */ + + writel(1, REGS_QOS_PXP0); /* OT_CTRL_EN =1 */ + writel(1, REGS_QOS_PXP1); /* OT_CTRL_EN =1 */ + + writel(0x0f020222, REGS_QOS_PXP0 + 0x50); /* WR, init = 2 with red flag */ + writel(0x0f020222, REGS_QOS_PXP1 + 0x50); /* WR, init = 2 with red flag */ + writel(0x0f020222, REGS_QOS_PXP0 + 0x60); /* rD, init = 2 with red flag */ + writel(0x0f020222, REGS_QOS_PXP1 + 0x60); /* rD, init = 2 with red flag */ + writel(0x0f020422, REGS_QOS_PXP0 + 0x70); /* tOTAL, init = 4 with red flag */ + writel(0x0f020422, REGS_QOS_PXP1 + 0x70); /* TOTAL, init = 4 with red flag */ + + writel(0xe080, IOMUXC_GPR_BASE_ADDR + 0x0034); /* EPDC AW/AR CACHE ENABLE */ +} + +int arch_cpu_init(void) +{ + init_aips(); + + /* Disable PDE bit of WMCR register */ + imx_set_wdog_powerdown(false); + + imx_set_pcie_phy_power_down(); + +#ifdef CONFIG_APBH_DMA + /* Start APBH DMA */ + mxs_dma_init(); +#endif + + set_epdc_qos(); + + return 0; +} + +#ifdef CONFIG_BOARD_POSTCLK_INIT +int board_postclk_init(void) +{ + /* + * We do not need to set LDO_SOC as i.mx6, since LDO_ARM and LDO_SOC + * does not exist. Check "Figure 7-9. i.MX7Dual Power Diagram" + */ + return 0; +} +#endif + +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + + serialnr->low = fuse->tester0; + serialnr->high = fuse->tester1; +} +#endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) + enum dcache_option option = DCACHE_WRITETHROUGH; +#else + enum dcache_option option = DCACHE_WRITEBACK; +#endif + + /* Avoid random hang when download by usb */ + invalidate_dcache_all(); + + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); + + /* Enable caching on OCRAM and ROM */ + mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR, + ROMCP_ARB_END_ADDR, + option); + mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, + IRAM_SIZE, + option); +} +#endif + +#if defined(CONFIG_FEC_MXC) +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[9]; + struct fuse_bank9_regs *fuse = + (struct fuse_bank9_regs *)bank->fuse_regs; + + if (0 == dev_id) { + u32 value = readl(&fuse->mac_addr1); + mac[0] = (value >> 8); + mac[1] = value; + + value = readl(&fuse->mac_addr0); + mac[2] = value >> 24; + mac[3] = value >> 16; + mac[4] = value >> 8; + mac[5] = value; + } else { + u32 value = readl(&fuse->mac_addr2); + mac[0] = value >> 24; + mac[1] = value >> 16; + mac[2] = value >> 8; + mac[3] = value; + + value = readl(&fuse->mac_addr1); + mac[4] = value >> 24; + mac[5] = value >> 16; + } +} +#endif + +int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) +{ + u32 stack, pc; + + if (!boot_private_data) + return 1; + + stack = *(u32 *)boot_private_data; + pc = *(u32 *)(boot_private_data + 4); + + /* Set the stack and pc to M4 bootROM */ + writel(stack, M4_BOOTROM_BASE_ADDR); + writel(pc, M4_BOOTROM_BASE_ADDR + 4); + + /* Enable M4 */ + setbits_le32(&src_reg->m4rcr, 0x00000008); + clrbits_le32(&src_reg->m4rcr, 0x00000001); + + return 0; +} + +int arch_auxiliary_core_check_up(u32 core_id) +{ + uint32_t val; + + val = readl(&src_reg->m4rcr); + if (val & 0x00000001) + return 0; /* assert in reset */ + + return 1; +} + +void boot_mode_apply(uint32_t cfg_val) +{ + uint32_t reg; + writel(cfg_val, &src_reg->gpr9); + reg = readl(&src_reg->gpr10); + if (cfg_val) + reg |= 1 << 28; + else + reg &= ~(1 << 28); + writel(reg, &src_reg->gpr10); +} + +void set_wdog_reset(struct wdog_regs *wdog) +{ + u32 reg = readw(&wdog->wcr); + /* + * Output WDOG_B signal to reset external pmic or POR_B decided by + * the board desgin. Without external reset, the peripherals/DDR/ + * PMIC are not reset, that may cause system working abnormal. + */ + reg = readw(&wdog->wcr); + reg |= 1 << 3; + /* + * WDZST bit is write-once only bit. Align this bit in kernel, + * otherwise kernel code will have no chance to set this bit. + */ + reg |= 1 << 0; + writew(reg, &wdog->wcr); +} + +/* + * cfg_val will be used for + * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] + * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0] + * to SBMR1, which will determine the boot device. + */ +const struct boot_mode soc_boot_modes[] = { + {"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)}, + {"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)}, + {"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)}, + {"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)}, + + {"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)}, + {"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)}, + /* 4 bit bus width */ + {"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, + {"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)}, + {"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)}, + {"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)}, + {"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)}, + {"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)}, + {NULL, 0}, +}; + +enum boot_device get_boot_device(void) +{ + struct bootrom_sw_info **p = + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR; + + enum boot_device boot_dev = SD1_BOOT; + u8 boot_type = (*p)->boot_dev_type; + u8 boot_instance = (*p)->boot_dev_instance; + + switch (boot_type) { + case BOOT_TYPE_SD: + boot_dev = boot_instance + SD1_BOOT; + break; + case BOOT_TYPE_MMC: + boot_dev = boot_instance + MMC1_BOOT; + break; + case BOOT_TYPE_NAND: + boot_dev = NAND_BOOT; + break; + case BOOT_TYPE_QSPI: + boot_dev = QSPI_BOOT; + break; + case BOOT_TYPE_WEIM: + boot_dev = WEIM_NOR_BOOT; + break; + case BOOT_TYPE_SPINOR: + boot_dev = SPI_NOR_BOOT; + break; + default: + break; + } + + return boot_dev; +} + +void s_init(void) +{ +#if !defined CONFIG_SPL_BUILD + /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ + asm volatile( + "mrc p15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #1 << 6\n" + "mcr p15, 0, r0, c1, c0, 1\n"); +#endif + /* clock configuration. */ + clock_init(); + + return; +} + +void reset_misc(void) +{ +#ifdef CONFIG_VIDEO_MXS + lcdif_power_down(); +#endif +} + +#ifdef CONFIG_IMX_UDC +void set_usb_phy1_clk(void) +{ + /* TODO */ +} +void enable_usb_phy1_clk(unsigned char enable) +{ +} + +void reset_usb_phy1(void) +{ + /* Reset USBPHY module */ + setbits_le32(&src_reg->usbophy1_rcr, 0x00000001); +} + +#endif diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index b9f1ca4..99bec53 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -7,20 +7,31 @@ # SPDX-License-Identifier: GPL-2.0+ #

-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 vf610)) +ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610)) obj-y = iomux-v3.o endif ifeq ($(SOC),$(filter $(SOC),mx5 mx6)) -obj-y += timer.o cpu.o speed.o +obj-y += cpu.o speed.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif -ifeq ($(SOC),$(filter $(SOC),mx6 mxs)) +ifeq ($(SOC),$(filter $(SOC),mx5)) +obj-y += timer.o +endif +ifeq ($(SOC),$(filter $(SOC),mx7)) +obj-y += cpu.o +obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o +obj-$(CONFIG_GPT_TIMER) += timer.o +obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o +endif +ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs)) obj-y += misc.o obj-$(CONFIG_SPL_BUILD) += spl.o endif ifeq ($(SOC),$(filter $(SOC),mx6)) obj-$(CONFIG_CMD_SATA) += sata.o obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o +obj-$(CONFIG_GPT_TIMER) += timer.o +obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o endif ifeq ($(SOC),$(filter $(SOC),vf610)) obj-y += ddrmc-vf610.o diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 2e803f3..3cd30e7 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -46,13 +46,26 @@ static char *get_reset_cause(void) case 0x00008: return "IPP USER"; case 0x00010: +#ifdef CONFIG_MX7 + return "WDOG1"; +#else return "WDOG"; +#endif case 0x00020: return "JTAG HIGH-Z"; case 0x00040: return "JTAG SW"; +#ifdef CONFIG_MX7 + case 0x00080: + return "WDOG3"; + case 0x00100: + return "WDOG4"; + case 0x00200: + return "TEMPSENSE"; +#else case 0x10000: return "WARM BOOT"; +#endif default: return "unknown reset"; } @@ -122,6 +135,8 @@ unsigned imx_ddr_size(void) const char *get_imx_type(u32 imxtype) { switch (imxtype) { + case MXC_CPU_MX7D: + return "7D"; /* Dual-core version of the mx7 */ case MXC_CPU_MX6Q: return "6Q"; /* Quad-core version of the mx6 */ case MXC_CPU_MX6D: @@ -236,6 +251,7 @@ int cpu_mmc_init(bd_t *bis) } #endif

+#ifndef CONFIG_MX7 u32 get_ahb_clk(void) { struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -247,6 +263,7 @@ u32 get_ahb_clk(void)

return get_periph_clk() / (ahb_podf + 1); } +#endif

void arch_preboot_os(void) { diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index c12556a..bc4a673 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -49,6 +49,8 @@ static inline int gpt_has_clk_source_osc(void) return 1;

return 0; +#elif defined(CONFIG_MX7) + return 1; #else return 0; #endif @@ -56,6 +58,9 @@ static inline int gpt_has_clk_source_osc(void)

static inline ulong gpt_get_clk(void) { +#if defined(CONFIG_MX7) + return MXC_HCLK >> 3; +#else #ifdef CONFIG_MXC_GPT_HCLK if (gpt_has_clk_source_osc()) return MXC_HCLK >> 3; @@ -64,6 +69,7 @@ static inline ulong gpt_get_clk(void) #else return MXC_CLK32; #endif +#endif } static inline unsigned long long tick_to_time(unsigned long long tick) { @@ -106,7 +112,8 @@ int timer_init(void) /* For DL/S, SX, set 24Mhz OSC Enable bit and prescaler */ if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO) || - is_cpu_type(MXC_CPU_MX6SX)) { + is_cpu_type(MXC_CPU_MX6SX) || + is_cpu_type(MXC_CPU_MX7D)) { i |= GPTCR_24MEN;

/* Produce 3Mhz clock */ diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 4715f4e..e0b4bc8 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -12,6 +12,7 @@ #define MXC_CPU_MX6Q 0x63 #define MXC_CPU_MX6D 0x64 #define MXC_CPU_MX6SOLO 0x65 /* dummy ID */ +#define MXC_CPU_MX7D 0x72

#define CS0_128 0 #define CS0_64M_CS1_64M 1 diff --git a/arch/arm/include/asm/arch-mx7/clock.h b/arch/arm/include/asm/arch-mx7/clock.h new file mode 100644 index 0000000..688d236 --- /dev/null +++ b/arch/arm/include/asm/arch-mx7/clock.h @@ -0,0 +1,348 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Author: + * Peng Fan Peng.Fan@freescale.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_CLOCK_H +#define _ASM_ARCH_CLOCK_H + +#include <common.h> +#include <asm/arch/crm_regs.h> + +#ifdef CONFIG_SYS_MX7_HCLK +#define MXC_HCLK CONFIG_SYS_MX7_HCLK +#else +#define MXC_HCLK 24000000 +#endif + +#ifdef CONFIG_SYS_MX7_CLK32 +#define MXC_CLK32 CONFIG_SYS_MX7_CLK32 +#else +#define MXC_CLK32 32768 +#endif + +/* Mainly for compatible to imx common code. */ +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_UART_CLK, + MXC_CSPI_CLK, + MXC_AXI_CLK, + MXC_DDR_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, + MXC_I2C_CLK, +}; + +/* PLL supported by i.mx7d */ +enum pll_clocks { + PLL_CORE, /* Core PLL */ + PLL_SYS, /* System PLL*/ + PLL_ENET, /* Enet PLL */ + PLL_AUDIO, /* Audio PLL */ + PLL_VIDEO, /* Video PLL*/ + PLL_DDR, /* Dram PLL */ + PLL_USB, /* USB PLL, fixed at 480MHZ */ +}; + +/* clk src for clock root gen */ +enum clk_root_src { + OSC_24M_CLK, + + PLL_ARM_MAIN_800M_CLK, + + PLL_SYS_MAIN_480M_CLK, + PLL_SYS_MAIN_240M_CLK, + PLL_SYS_MAIN_120M_CLK, + PLL_SYS_PFD0_392M_CLK, + PLL_SYS_PFD0_196M_CLK, + PLL_SYS_PFD1_332M_CLK, + PLL_SYS_PFD1_166M_CLK, + PLL_SYS_PFD2_270M_CLK, + PLL_SYS_PFD2_135M_CLK, + PLL_SYS_PFD3_CLK, + PLL_SYS_PFD4_CLK, + PLL_SYS_PFD5_CLK, + PLL_SYS_PFD6_CLK, + PLL_SYS_PFD7_CLK, + + PLL_ENET_MAIN_500M_CLK, + PLL_ENET_MAIN_250M_CLK, + PLL_ENET_MAIN_125M_CLK, + PLL_ENET_MAIN_100M_CLK, + PLL_ENET_MAIN_50M_CLK, + PLL_ENET_MAIN_40M_CLK, + PLL_ENET_MAIN_25M_CLK, + + PLL_DRAM_MAIN_1066M_CLK, + PLL_DRAM_MAIN_533M_CLK, + + PLL_AUDIO_MAIN_CLK, + PLL_VIDEO_MAIN_CLK, + + PLL_USB_MAIN_480M_CLK, /* fixed at 480MHZ */ + + EXT_CLK_1, + EXT_CLK_2, + EXT_CLK_3, + EXT_CLK_4, + + REF_1M_CLK, + OSC_32K_CLK, +}; + +/* + * Clock root index + */ +enum clk_root_index { + ARM_A7_CLK_ROOT = 0, + ARM_M4_CLK_ROOT = 1, + ARM_M0_CLK_ROOT = 2, + MAIN_AXI_CLK_ROOT = 16, + DISP_AXI_CLK_ROOT = 17, + ENET_AXI_CLK_ROOT = 18, + NAND_USDHC_BUS_CLK_ROOT = 19, + AHB_CLK_ROOT = 32, + DRAM_PHYM_CLK_ROOT = 48, + DRAM_CLK_ROOT = 49, + DRAM_PHYM_ALT_CLK_ROOT = 64, + DRAM_ALT_CLK_ROOT = 65, + USB_HSIC_CLK_ROOT = 66, + PCIE_CTRL_CLK_ROOT = 67, + PCIE_PHY_CLK_ROOT = 68, + EPDC_PIXEL_CLK_ROOT = 69, + LCDIF_PIXEL_CLK_ROOT = 70, + MIPI_DSI_EXTSER_CLK_ROOT = 71, + MIPI_CSI_WARP_CLK_ROOT = 72, + MIPI_DPHY_REF_CLK_ROOT = 73, + SAI1_CLK_ROOT = 74, + SAI2_CLK_ROOT = 75, + SAI3_CLK_ROOT = 76, + SPDIF_CLK_ROOT = 77, + ENET1_REF_CLK_ROOT = 78, + ENET1_TIME_CLK_ROOT = 79, + ENET2_REF_CLK_ROOT = 80, + ENET2_TIME_CLK_ROOT = 81, + ENET_PHY_REF_CLK_ROOT = 82, + EIM_CLK_ROOT = 83, + NAND_CLK_ROOT = 84, + QSPI_CLK_ROOT = 85, + USDHC1_CLK_ROOT = 86, + USDHC2_CLK_ROOT = 87, + USDHC3_CLK_ROOT = 88, + CAN1_CLK_ROOT = 89, + CAN2_CLK_ROOT = 90, + I2C1_CLK_ROOT = 91, + I2C2_CLK_ROOT = 92, + I2C3_CLK_ROOT = 93, + I2C4_CLK_ROOT = 94, + UART1_CLK_ROOT = 95, + UART2_CLK_ROOT = 96, + UART3_CLK_ROOT = 97, + UART4_CLK_ROOT = 98, + UART5_CLK_ROOT = 99, + UART6_CLK_ROOT = 100, + UART7_CLK_ROOT = 101, + ECSPI1_CLK_ROOT = 102, + ECSPI2_CLK_ROOT = 103, + ECSPI3_CLK_ROOT = 104, + ECSPI4_CLK_ROOT = 105, + PWM1_CLK_ROOT = 106, + PWM2_CLK_ROOT = 107, + PWM3_CLK_ROOT = 108, + PWM4_CLK_ROOT = 109, + FLEXTIMER1_CLK_ROOT = 110, + FLEXTIMER2_CLK_ROOT = 111, + SIM1_CLK_ROOT = 112, + SIM2_CLK_ROOT = 113, + GPT1_CLK_ROOT = 114, + GPT2_CLK_ROOT = 115, + GPT3_CLK_ROOT = 116, + GPT4_CLK_ROOT = 117, + TRACE_CLK_ROOT = 118, + WDOG_CLK_ROOT = 119, + CSI_MCLK_CLK_ROOT = 120, + AUDIO_MCLK_CLK_ROOT = 121, + WRCLK_CLK_ROOT = 122, + IPP_DO_CLKO1 = 123, + IPP_DO_CLKO2 = 124, + + CLK_ROOT_MAX, +}; + +struct clk_root_setting { + enum clk_root_index root; + u32 setting; +}; + +/* + * CCGR mapping + */ +enum clk_ccgr_index { + CCGR_CPU = 0, + CCGR_M4 = 1, + CCGR_SIM_MAIN = 4, + CCGR_SIM_DISPLAY = 5, + CCGR_SIM_ENET = 6, + CCGR_SIM_M = 7, + CCGR_SIM_S = 8, + CCGR_SIM_WAKEUP = 9, + CCGR_IPMUX1 = 10, + CCGR_IPMUX2 = 11, + CCGR_IPMUX3 = 12, + CCGR_ROM = 16, + CCGR_OCRAM = 17, + CCGR_OCRAM_S = 18, + CCGR_DRAM = 19, + CCGR_RAWNAND = 20, + CCGR_QSPI = 21, + CCGR_WEIM = 22, + CCGR_ADC = 32, + CCGR_ANATOP = 33, + CCGR_SCTR = 34, + CCGR_OCOTP = 35, + CCGR_CAAM = 36, + CCGR_SNVS = 37, + CCGR_RDC = 38, + CCGR_MU = 39, + CCGR_HS = 40, + CCGR_DVFS = 41, + CCGR_QOS = 42, + CCGR_QOS_DISPMIX = 43, + CCGR_QOS_MEGAMIX = 44, + CCGR_CSU = 45, + CCGR_DBGMON = 46, + CCGR_DEBUG = 47, + CCGR_TRACE = 48, + CCGR_SEC_DEBUG = 49, + CCGR_SEMA1 = 64, + CCGR_SEMA2 = 65, + CCGR_PERFMON1 = 68, + CCGR_PERFMON2 = 69, + CCGR_SDMA = 72, + CCGR_CSI = 73, + CCGR_EPDC = 74, + CCGR_LCDIF = 75, + CCGR_PXP = 76, + CCGR_PCIE = 96, + CCGR_MIPI_CSI = 100, + CCGR_MIPI_DSI = 101, + CCGR_MIPI_MEM_PHY = 102, + CCGR_USB_CTRL = 104, + CCGR_USB_HSIC = 105, + CCGR_USB_PHY1 = 106, + CCGR_USB_PHY2 = 107, + CCGR_USDHC1 = 108, + CCGR_USDHC2 = 109, + CCGR_USDHC3 = 110, + CCGR_ENET1 = 112, + CCGR_ENET2 = 113, + CCGR_CAN1 = 116, + CCGR_CAN2 = 117, + CCGR_ECSPI1 = 120, + CCGR_ECSPI2 = 121, + CCGR_ECSPI3 = 122, + CCGR_ECSPI4 = 123, + CCGR_GPT1 = 124, + CCGR_GPT2 = 125, + CCGR_GPT3 = 126, + CCGR_GPT4 = 127, + CCGR_FTM1 = 128, + CCGR_FTM2 = 129, + CCGR_PWM1 = 132, + CCGR_PWM2 = 133, + CCGR_PWM3 = 134, + CCGR_PWM4 = 135, + CCGR_I2C1 = 136, + CCGR_I2C2 = 137, + CCGR_I2C3 = 138, + CCGR_I2C4 = 139, + CCGR_SAI1 = 140, + CCGR_SAI2 = 141, + CCGR_SAI3 = 142, + CCGR_SIM1 = 144, + CCGR_SIM2 = 145, + CCGR_UART1 = 148, + CCGR_UART2 = 149, + CCGR_UART3 = 150, + CCGR_UART4 = 151, + CCGR_UART5 = 152, + CCGR_UART6 = 153, + CCGR_UART7 = 154, + CCGR_WDOG1 = 156, + CCGR_WDOG2 = 157, + CCGR_WDOG3 = 158, + CCGR_WDOG4 = 159, + CCGR_GPIO1 = 160, + CCGR_GPIO2 = 161, + CCGR_GPIO3 = 162, + CCGR_GPIO4 = 163, + CCGR_GPIO5 = 164, + CCGR_GPIO6 = 165, + CCGR_GPIO7 = 166, + CCGR_IOMUX = 168, + CCGR_IOMUX_LPSR = 169, + CCGR_KPP = 170, + + CCGR_SKIP, + CCGR_MAX, +}; + +/* Clock root channel */ +enum clk_root_type { + CCM_CORE_CHANNEL, + CCM_BUS_CHANNEL, + CCM_AHB_CHANNEL, + CCM_DRAM_PHYM_CHANNEL, + CCM_DRAM_CHANNEL, + CCM_IP_CHANNEL, +}; + +#include <asm/arch/clock_slice.h> + +/* + * entry: the clock root index + * type: ccm channel + * src_mux: each entry corresponding to the clock src, detailed info in CCM RM + */ +struct clk_root_map { + enum clk_root_index entry; + enum clk_root_type type; + uint8_t src_mux[8]; +}; + +enum enet_freq { + ENET_25MHz, + ENET_50MHz, + ENET_125MHz, +}; + +u32 get_root_clk(enum clk_root_index clock_id); +u32 mxc_get_clock(enum mxc_clock clk); +u32 imx_get_uartclk(void); +u32 imx_get_fecclk(void); +void clock_init(void); +#ifdef CONFIG_SYS_I2C_MXC +int enable_i2c_clk(unsigned char enable, unsigned i2c_num); +#endif +#ifdef CONFIG_FEC_MXC +int set_clk_enet(enum enet_freq type); +#endif +int set_clk_qspi(void); +int set_clk_nand(void); +#ifdef CONFIG_MXC_OCOTP +void enable_ocotp_clk(unsigned char enable); +#endif +void enable_usboh3_clk(unsigned char enable); +#ifdef CONFIG_SECURE_BOOT +void hab_caam_clock_enable(unsigned char enable); +#endif +void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq); +void enable_thermal_clk(void); +#endif diff --git a/arch/arm/include/asm/arch-mx7/clock_slice.h b/arch/arm/include/asm/arch-mx7/clock_slice.h new file mode 100644 index 0000000..6ede0cd --- /dev/null +++ b/arch/arm/include/asm/arch-mx7/clock_slice.h @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * Author: + * Peng Fan Peng.Fan@freescale.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_CLOCK_SLICE_H +#define _ASM_ARCH_CLOCK_SLICE_H + +enum root_pre_div { + CLK_ROOT_PRE_DIV1 = 0, + CLK_ROOT_PRE_DIV2, + CLK_ROOT_PRE_DIV3, + CLK_ROOT_PRE_DIV4, + CLK_ROOT_PRE_DIV5, + CLK_ROOT_PRE_DIV6, + CLK_ROOT_PRE_DIV7, + CLK_ROOT_PRE_DIV8, +}; + +enum root_post_div { + CLK_ROOT_POST_DIV1 = 0, + CLK_ROOT_POST_DIV2, + CLK_ROOT_POST_DIV3, + CLK_ROOT_POST_DIV4, + CLK_ROOT_POST_DIV5, + CLK_ROOT_POST_DIV6, + CLK_ROOT_POST_DIV7, + CLK_ROOT_POST_DIV8, + CLK_ROOT_POST_DIV9, + CLK_ROOT_POST_DIV10, + CLK_ROOT_POST_DIV11, + CLK_ROOT_POST_DIV12, + CLK_ROOT_POST_DIV13, + CLK_ROOT_POST_DIV14, + CLK_ROOT_POST_DIV15, + CLK_ROOT_POST_DIV16, + CLK_ROOT_POST_DIV17, + CLK_ROOT_POST_DIV18, + CLK_ROOT_POST_DIV19, + CLK_ROOT_POST_DIV20, + CLK_ROOT_POST_DIV21, + CLK_ROOT_POST_DIV22, + CLK_ROOT_POST_DIV23, + CLK_ROOT_POST_DIV24, + CLK_ROOT_POST_DIV25, + CLK_ROOT_POST_DIV26, + CLK_ROOT_POST_DIV27, + CLK_ROOT_POST_DIV28, + CLK_ROOT_POST_DIV29, + CLK_ROOT_POST_DIV30, + CLK_ROOT_POST_DIV31, + CLK_ROOT_POST_DIV32, + CLK_ROOT_POST_DIV33, + CLK_ROOT_POST_DIV34, + CLK_ROOT_POST_DIV35, + CLK_ROOT_POST_DIV36, + CLK_ROOT_POST_DIV37, + CLK_ROOT_POST_DIV38, + CLK_ROOT_POST_DIV39, + CLK_ROOT_POST_DIV40, + CLK_ROOT_POST_DIV41, + CLK_ROOT_POST_DIV42, + CLK_ROOT_POST_DIV43, + CLK_ROOT_POST_DIV44, + CLK_ROOT_POST_DIV45, + CLK_ROOT_POST_DIV46, + CLK_ROOT_POST_DIV47, + CLK_ROOT_POST_DIV48, + CLK_ROOT_POST_DIV49, + CLK_ROOT_POST_DIV50, + CLK_ROOT_POST_DIV51, + CLK_ROOT_POST_DIV52, + CLK_ROOT_POST_DIV53, + CLK_ROOT_POST_DIV54, + CLK_ROOT_POST_DIV55, + CLK_ROOT_POST_DIV56, + CLK_ROOT_POST_DIV57, + CLK_ROOT_POST_DIV58, + CLK_ROOT_POST_DIV59, + CLK_ROOT_POST_DIV60, + CLK_ROOT_POST_DIV61, + CLK_ROOT_POST_DIV62, + CLK_ROOT_POST_DIV63, + CLK_ROOT_POST_DIV64, +}; + +enum root_auto_div { + CLK_ROOT_AUTO_DIV1 = 0, + CLK_ROOT_AUTO_DIV2, + CLK_ROOT_AUTO_DIV4, + CLK_ROOT_AUTO_DIV8, + CLK_ROOT_AUTO_DIV16, +}; + +int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src); +int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src); +int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div); +int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div); +int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div); +int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div); +int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div, + int auto_en); +int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div, + int *auto_en); +int clock_get_target_val(enum clk_root_index clock_id, u32 *val); +int clock_set_target_val(enum clk_root_index clock_id, u32 val); +int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div, + enum root_post_div post_div, enum clk_root_src clock_src); +int clock_root_enabled(enum clk_root_index clock_id); + +int clock_enable(enum clk_ccgr_index index, bool enable); +#endif diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h new file mode 100644 index 0000000..8a68a39 --- /dev/null +++ b/arch/arm/include/asm/arch-mx7/crm_regs.h @@ -0,0 +1,2813 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * Author: + * Peng Fan Peng.Fan@freescale.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_ARM_MACH_MX7_CCM_REGS_H__ +#define __ARCH_ARM_MACH_MX7_CCM_REGS_H__ + +#include <asm/arch/imx-regs.h> +#include <asm/io.h> + +#define CCM_GPR0_OFFSET 0x0 +#define CCM_OBSERVE0_OFFSET 0x0400 +#define CCM_SCTRL0_OFFSET 0x0800 +#define CCM_CCGR0_OFFSET 0x4000 +#define CCM_ROOT0_TARGET_OFFSET 0x8000 + +#ifndef __ASSEMBLY__ + +struct mxc_ccm_ccgr { + uint32_t ccgr; + uint32_t ccgr_set; + uint32_t ccgr_clr; + uint32_t ccgr_tog; +}; + +struct mxc_ccm_root_slice { + uint32_t target_root; + uint32_t target_root_set; + uint32_t target_root_clr; + uint32_t target_root_tog; + uint32_t reserved_0[4]; + uint32_t post; + uint32_t post_root_set; + uint32_t post_root_clr; + uint32_t post_root_tog; + uint32_t pre; + uint32_t pre_root_set; + uint32_t pre_root_clr; + uint32_t pre_root_tog; + uint32_t reserved_1[12]; + uint32_t access_ctrl; + uint32_t access_ctrl_root_set; + uint32_t access_ctrl_root_clr; + uint32_t access_ctrl_root_tog; +}; + +/** CCM - Peripheral register structure */ +struct mxc_ccm_reg { + uint32_t gpr0; + uint32_t gpr0_set; + uint32_t gpr0_clr; + uint32_t gpr0_tog; + uint32_t reserved_0[4092]; + struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */ + uint32_t reserved_1[3332]; + struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */ + +}; + +struct mxc_ccm_anatop_reg { + uint32_t ctrl_24m; /* offset 0x0000 */ + uint32_t ctrl_24m_set; + uint32_t ctrl_24m_clr; + uint32_t ctrl_24m_tog; + uint32_t rcosc_config0; /* offset 0x0010 */ + uint32_t rcosc_config0_set; + uint32_t rcosc_config0_clr; + uint32_t rcosc_config0_tog; + uint32_t rcosc_config1; /* offset 0x0020 */ + uint32_t rcosc_config1_set; + uint32_t rcosc_config1_clr; + uint32_t rcosc_config1_tog; + uint32_t rcosc_config2; /* offset 0x0030 */ + uint32_t rcosc_config2_set; + uint32_t rcosc_config2_clr; + uint32_t rcosc_config2_tog; + uint8_t reserved_0[16]; + uint32_t osc_32k; /* offset 0x0050 */ + uint32_t osc_32k_set; + uint32_t osc_32k_clr; + uint32_t osc_32k_tog; + uint32_t pll_arm; /* offset 0x0060 */ + uint32_t pll_arm_set; + uint32_t pll_arm_clr; + uint32_t pll_arm_tog; + uint32_t pll_ddr; /* offset 0x0070 */ + uint32_t pll_ddr_set; + uint32_t pll_ddr_clr; + uint32_t pll_ddr_tog; + uint32_t pll_ddr_ss; /* offset 0x0080 */ + uint8_t reserved_1[12]; + uint32_t pll_ddr_num; /* offset 0x0090 */ + uint8_t reserved_2[12]; + uint32_t pll_ddr_denom; /* offset 0x00a0 */ + uint8_t reserved_3[12]; + uint32_t pll_480; /* offset 0x00b0 */ + uint32_t pll_480_set; + uint32_t pll_480_clr; + uint32_t pll_480_tog; + uint32_t pfd_480a; /* offset 0x00c0 */ + uint32_t pfd_480a_set; + uint32_t pfd_480a_clr; + uint32_t pfd_480a_tog; + uint32_t pfd_480b; /* offset 0x00d0 */ + uint32_t pfd_480b_set; + uint32_t pfd_480b_clr; + uint32_t pfd_480b_tog; + uint32_t pll_enet; /* offset 0x00e0 */ + uint32_t pll_enet_set; + uint32_t pll_enet_clr; + uint32_t pll_enet_tog; + uint32_t pll_audio; /* offset 0x00f0 */ + uint32_t pll_audio_set; + uint32_t pll_audio_clr; + uint32_t pll_audio_tog; + uint32_t pll_audio_ss; /* offset 0x0100 */ + uint8_t reserved_4[12]; + uint32_t pll_audio_num; /* offset 0x0110 */ + uint8_t reserved_5[12]; + uint32_t pll_audio_denom; /* offset 0x0120 */ + uint8_t reserved_6[12]; + uint32_t pll_video; /* offset 0x0130 */ + uint32_t pll_video_set; + uint32_t pll_video_clr; + uint32_t pll_video_tog; + uint32_t pll_video_ss; /* offset 0x0140 */ + uint8_t reserved_7[12]; + uint32_t pll_video_num; /* offset 0x0150 */ + uint8_t reserved_8[12]; + uint32_t pll_video_denom; /* offset 0x0160 */ + uint8_t reserved_9[12]; + uint32_t clk_misc0; /* offset 0x0170 */ + uint32_t clk_misc0_set; + uint32_t clk_misc0_clr; + uint32_t clk_misc0_tog; + uint32_t clk_rsvd; /* offset 0x0180 */ + uint8_t reserved_10[124]; + uint32_t reg_1p0a; /* offset 0x0200 */ + uint32_t reg_1p0a_set; + uint32_t reg_1p0a_clr; + uint32_t reg_1p0a_tog; + uint32_t reg_1p0d; /* offsest 0x0210 */ + uint32_t reg_1p0d_set; + uint32_t reg_1p0d_clr; + uint32_t reg_1p0d_tog; + uint32_t reg_hsic_1p2; /* offset 0x0220 */ + uint32_t reg_hsic_1p2_set; + uint32_t reg_hsic_1p2_clr; + uint32_t reg_hsic_1p2_tog; + uint32_t reg_lpsr_1p0; /* offset 0x0230 */ + uint32_t reg_lpsr_1p0_set; + uint32_t reg_lpsr_1p0_clr; + uint32_t reg_lpsr_1p0_tog; + uint32_t reg_3p0; /* offset 0x0240 */ + uint32_t reg_3p0_set; + uint32_t reg_3p0_clr; + uint32_t reg_3p0_tog; + uint32_t reg_snvs; /* offset 0x0250 */ + uint32_t reg_snvs_set; + uint32_t reg_snvs_clr; + uint32_t reg_snvs_tog; + uint32_t analog_debug_misc0; /* offset 0x0260 */ + uint32_t analog_debug_misc0_set; + uint32_t analog_debug_misc0_clr; + uint32_t analog_debug_misc0_tog; + uint32_t ref; /* offset 0x0270 */ + uint32_t ref_set; + uint32_t ref_clr; + uint32_t ref_tog; + uint8_t reserved_11[128]; + uint32_t tempsense0; /* offset 0x0300 */ + uint32_t tempsense0_set; + uint32_t tempsense0_clr; + uint32_t tempsense0_tog; + uint32_t tempsense1; /* offset 0x0310 */ + uint32_t tempsense1_set; + uint32_t tempsense1_clr; + uint32_t tempsense1_tog; + uint32_t tempsense_trim; /* offset 0x0320 */ + uint32_t tempsense_trim_set; + uint32_t tempsense_trim_clr; + uint32_t tempsense_trim_tog; + uint32_t lowpwr_ctrl; /* offset 0x0330 */ + uint32_t lowpwr_ctrl_set; + uint32_t lowpwr_ctrl_clr; + uint32_t lowpwr_ctrl_tog; + uint32_t snvs_tamper_offset_ctrl; /* offset 0x0340 */ + uint32_t snvs_tamper_offset_ctrl_set; + uint32_t snvs_tamper_offset_ctrl_clr; + uint32_t snvs_tamper_offset_ctrl_tog; + uint32_t snvs_tamper_pull_ctrl; /* offset 0x0350 */ + uint32_t snvs_tamper_pull_ctrl_set; + uint32_t snvs_tamper_pull_ctrl_clr; + uint32_t snvs_tamper_pull_ctrl_tog; + uint32_t snvs_test; /* offset 0x0360 */ + uint32_t snvs_test_set; + uint32_t snvs_test_clr; + uint32_t snvs_test_tog; + uint32_t snvs_tamper_trim_ctrl; /* offset 0x0370 */ + uint32_t snvs_tamper_trim_ctrl_set; + uint32_t snvs_tamper_trim_ctrl_ctrl; + uint32_t snvs_tamper_trim_ctrl_tog; + uint32_t snvs_misc_ctrl; /* offset 0x0380 */ + uint32_t snvs_misc_ctrl_set; + uint32_t snvs_misc_ctrl_clr; + uint32_t snvs_misc_ctrl_tog; + uint8_t reserved_12[112]; + uint32_t misc; /* offset 0x0400 */ + uint8_t reserved_13[252]; + uint32_t adc0; /* offset 0x0500 */ + uint8_t reserved_14[12]; + uint32_t adc1; /* offset 0x0510 */ + uint8_t reserved_15[748]; + uint32_t digprog; /* offset 0x0800 */ +}; +#endif + +#define ANADIG_CLK_MISC0_PFD_480_AUTOGATE_EN_MASK (0x01 << 17) + +#define ANADIG_PLL_LOCK 0x80000000 + +#define ANADIG_PLL_ARM_PWDN_MASK (0x01 << 12) +#define ANADIG_PLL_480_PWDN_MASK (0x01 << 12) +#define ANADIG_PLL_DDR_PWDN_MASK (0x01 << 20) +#define ANADIG_PLL_ENET_PWDN_MASK (0x01 << 5) +#define ANADIG_PLL_VIDEO_PWDN_MASK (0x01 << 12) + + +#define ANATOP_PFD480B_PFD4_FRAC_MASK 0x0000003f +#define ANATOP_PFD480B_PFD4_FRAC_320M_VAL 0x0000001B +#define ANATOP_PFD480B_PFD4_FRAC_392M_VAL 0x00000016 +#define ANATOP_PFD480B_PFD4_FRAC_432M_VAL 0x00000014 + +/* PLL_ARM Bit Fields */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK 0x7F +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_ARM_HALF_LF_MASK 0x80 +#define CCM_ANALOG_PLL_ARM_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_MASK 0x100 +#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_ARM_HALF_CP_MASK 0x200 +#define CCM_ANALOG_PLL_ARM_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_MASK 0x400 +#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_MASK 0x800 +#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK 0x1000 +#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_MASK 0x2000 +#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK 0xC000 +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_ARM_BYPASS_MASK 0x10000 +#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_ARM_LVDS_SEL_MASK 0x20000 +#define CCM_ANALOG_PLL_ARM_LVDS_SEL_SHIFT 17 +#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_MASK 0x40000 +#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_SHIFT 18 +#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK 0x80000 +#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT 19 +#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_MASK 0x100000 +#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_SHIFT 20 +#define CCM_ANALOG_PLL_ARM_RSVD0_MASK 0x7FE00000 +#define CCM_ANALOG_PLL_ARM_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_ARM_LOCK_MASK 0x80000000 +#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT 31 + +/* PLL_DDR Bit Fields */ +#define CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK 0x7F +#define CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_DDR_HALF_LF_MASK 0x80 +#define CCM_ANALOG_PLL_DDR_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_MASK 0x100 +#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_DDR_HALF_CP_MASK 0x200 +#define CCM_ANALOG_PLL_DDR_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_MASK 0x400 +#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_MASK 0x800 +#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK 0x1000 +#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_SHIFT 12 +#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_MASK 0x2000 +#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_MASK 0xC000 +#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_DDR_BYPASS_MASK 0x10000 +#define CCM_ANALOG_PLL_DDR_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_MASK 0x20000 +#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_MASK 0x40000 +#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_MASK 0x80000 +#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_SHIFT 19 +#define CCM_ANALOG_PLL_DDR_POWERDOWN_MASK 0x100000 +#define CCM_ANALOG_PLL_DDR_POWERDOWN_SHIFT 20 +#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK 0x600000 +#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_SHIFT 21 +#define CCM_ANALOG_PLL_DDR_RSVD1_MASK 0x7F800000 +#define CCM_ANALOG_PLL_DDR_RSVD1_SHIFT 23 +#define CCM_ANALOG_PLL_DDR_LOCK_MASK 0x80000000 +#define CCM_ANALOG_PLL_DDR_LOCK_SHIFT 31 + +/* PLL_480 Bit Fields */ +#define CCM_ANALOG_PLL_480_DIV_SELECT_MASK 0x1 +#define CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_480_RSVD0_MASK 0xE +#define CCM_ANALOG_PLL_480_RSVD0_SHIFT 1 +#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK 0x10 +#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_SHIFT 4 +#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK 0x20 +#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_SHIFT 5 +#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK 0x40 +#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_SHIFT 6 +#define CCM_ANALOG_PLL_480_HALF_LF_MASK 0x80 +#define CCM_ANALOG_PLL_480_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_480_DOUBLE_LF_MASK 0x100 +#define CCM_ANALOG_PLL_480_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_480_HALF_CP_MASK 0x200 +#define CCM_ANALOG_PLL_480_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_480_DOUBLE_CP_MASK 0x400 +#define CCM_ANALOG_PLL_480_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_MASK 0x800 +#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_480_POWERDOWN_MASK 0x1000 +#define CCM_ANALOG_PLL_480_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_480_ENABLE_CLK_MASK 0x2000 +#define CCM_ANALOG_PLL_480_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_MASK 0xC000 +#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_480_BYPASS_MASK 0x10000 +#define CCM_ANALOG_PLL_480_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_MASK 0x20000 +#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_SHIFT 17 +#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_MASK 0x40000 +#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_SHIFT 18 +#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_MASK 0x80000 +#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_SHIFT 19 +#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_MASK 0x100000 +#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_SHIFT 20 +#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_MASK 0x200000 +#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_SHIFT 21 +#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_MASK 0x400000 +#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_SHIFT 22 +#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_MASK 0x800000 +#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_SHIFT 23 +#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_MASK 0x1000000 +#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_MASK 0x2000000 +#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_SHIFT 25 +#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK 0x4000000 +#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_SHIFT 26 +#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK 0x8000000 +#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_SHIFT 27 +#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK 0x10000000 +#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_SHIFT 28 +#define CCM_ANALOG_PLL_480_RSVD1_MASK 0x60000000 +#define CCM_ANALOG_PLL_480_RSVD1_SHIFT 29 +#define CCM_ANALOG_PLL_480_LOCK_MASK 0x80000000 +#define CCM_ANALOG_PLL_480_LOCK_SHIFT 31 + +/* PFD_480A Bit Fields */ +#define CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK 0x3F +#define CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT 0 +#define CCM_ANALOG_PFD_480A_PFD0_STABLE_MASK 0x40 +#define CCM_ANALOG_PFD_480A_PFD0_STABLE_SHIFT 6 +#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK 0x80 +#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_SHIFT 7 +#define CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK 0x3F00 +#define CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT 8 +#define CCM_ANALOG_PFD_480A_PFD1_STABLE_MASK 0x4000 +#define CCM_ANALOG_PFD_480A_PFD1_STABLE_SHIFT 14 +#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK 0x8000 +#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_SHIFT 15 +#define CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK 0x3F0000 +#define CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT 16 +#define CCM_ANALOG_PFD_480A_PFD2_STABLE_MASK 0x400000 +#define CCM_ANALOG_PFD_480A_PFD2_STABLE_SHIFT 22 +#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK 0x800000 +#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_SHIFT 23 +#define CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK 0x3F000000 +#define CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT 24 +#define CCM_ANALOG_PFD_480A_PFD3_STABLE_MASK 0x40000000 +#define CCM_ANALOG_PFD_480A_PFD3_STABLE_SHIFT 30 +#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK 0x80000000 +#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_SHIFT 31 +/* PFD_480B Bit Fields */ +#define CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK 0x3F +#define CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT 0 +#define CCM_ANALOG_PFD_480B_PFD4_STABLE_MASK 0x40 +#define CCM_ANALOG_PFD_480B_PFD4_STABLE_SHIFT 6 +#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK 0x80 +#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_SHIFT 7 +#define CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK 0x3F00 +#define CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT 8 +#define CCM_ANALOG_PFD_480B_PFD5_STABLE_MASK 0x4000 +#define CCM_ANALOG_PFD_480B_PFD5_STABLE_SHIFT 14 +#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK 0x8000 +#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_SHIFT 15 +#define CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK 0x3F0000 +#define CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT 16 +#define CCM_ANALOG_PFD_480B_PFD6_STABLE_MASK 0x400000 +#define CCM_ANALOG_PFD_480B_PFD6_STABLE_SHIFT 22 +#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK 0x800000 +#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_SHIFT 23 +#define CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK 0x3F000000 +#define CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT 24 +#define CCM_ANALOG_PFD_480B_PFD7_STABLE_MASK 0x40000000 +#define CCM_ANALOG_PFD_480B_PFD7_STABLE_SHIFT 30 +#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK 0x80000000 +#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_SHIFT 31 + +/* PLL_ENET Bit Fields */ +#define CCM_ANALOG_PLL_ENET_HALF_LF_MASK 0x1 +#define CCM_ANALOG_PLL_ENET_HALF_LF_SHIFT 0 +#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_MASK 0x2 +#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_SHIFT 1 +#define CCM_ANALOG_PLL_ENET_HALF_CP_MASK 0x4 +#define CCM_ANALOG_PLL_ENET_HALF_CP_SHIFT 2 +#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_MASK 0x8 +#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_SHIFT 3 +#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_MASK 0x10 +#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_SHIFT 4 +#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK 0x20 +#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT 5 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK 0x40 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_SHIFT 6 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK 0x80 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_SHIFT 7 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK 0x100 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_SHIFT 8 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK 0x200 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_SHIFT 9 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK 0x400 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_SHIFT 10 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK 0x800 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_SHIFT 11 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK 0x1000 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_SHIFT 12 +#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_MASK 0x2000 +#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_SHIFT 13 +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK 0xC000 +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_ENET_BYPASS_MASK 0x10000 +#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_MASK 0x20000 +#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK 0x40000 +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_ENET_RSVD1_MASK 0x7FF80000 +#define CCM_ANALOG_PLL_ENET_RSVD1_SHIFT 19 +#define CCM_ANALOG_PLL_ENET_LOCK_MASK 0x80000000 +#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT 31 + +/* PLL_AUDIO Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_AUDIO_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_AUDIO_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_AUDIO_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_AUDIO_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_AUDIO_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_AUDIO_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_RSVD1_MASK) +#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT 31 +/* PLL_AUDIO_SET Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT 31 +/* PLL_AUDIO_CLR Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT 31 +/* PLL_AUDIO_TOG Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT 31 +/* PLL_AUDIO_SS Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK 0x7FFFu +#define CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_SS_STEP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK) +#define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_MASK 0x8000u +#define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_SHIFT 15 +#define CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK 0xFFFF0000u +#define CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT 16 +#define CCM_ANALOG_PLL_AUDIO_SS_STOP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK) +/* PLL_AUDIO_NUM Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK 0x3FFFFFFFu +#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) +#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK 0xC0000000u +#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT 30 +#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK) +/* PLL_AUDIO_DENOM Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK 0x3FFFFFFFu +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) +#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK 0xC0000000u +#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT 30 +#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK) +/* PLL_VIDEO Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_VIDEO_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_VIDEO_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_VIDEO_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_VIDEO_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_VIDEO_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_VIDEO_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_RSVD1_MASK) +#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT 31 +/* PLL_VIDEO_SET Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT 31 +/* PLL_VIDEO_CLR Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT 31 +/* PLL_VIDEO_TOG Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT 31 +/* PLL_VIDEO_SS Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK 0x7FFFu +#define CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_SS_STEP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK) +#define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_MASK 0x8000u +#define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_SHIFT 15 +#define CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK 0xFFFF0000u +#define CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT 16 +#define CCM_ANALOG_PLL_VIDEO_SS_STOP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK) +/* PLL_VIDEO_NUM Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK 0x3FFFFFFFu +#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) +#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK 0xC0000000u +#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT 30 +#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK) +/* PLL_VIDEO_DENOM Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK 0x3FFFFFFFu +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) +#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK 0xC0000000u +#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT 30 +#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK) +/* CLK_MISC0 Bit Fields */ +#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK 0x1Fu +#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT 0 +#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_MASK 0x20u +#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_SHIFT 5 +#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_MASK 0x40u +#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_SHIFT 6 +#define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_MASK 0x80u +#define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_SHIFT 7 +#define CCM_ANALOG_CLK_MISC0_RSVD0_MASK 0xFFFFFF00u +#define CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT 8 +#define CCM_ANALOG_CLK_MISC0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_RSVD0_MASK) +/* CLK_MISC0_SET Bit Fields */ +#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK 0x1Fu +#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT 0 +#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_MASK 0x20u +#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_SHIFT 5 +#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_MASK 0x40u +#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_SHIFT 6 +#define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_MASK 0x80u +#define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_SHIFT 7 +#define CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK 0xFFFFFF00u +#define CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT 8 +#define CCM_ANALOG_CLK_MISC0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK) +/* CLK_MISC0_CLR Bit Fields */ +#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK 0x1Fu +#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT 0 +#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_MASK 0x20u +#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_SHIFT 5 +#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_MASK 0x40u +#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_SHIFT 6 +#define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_MASK 0x80u +#define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_SHIFT 7 +#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK 0xFFFFFF00u +#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT 8 +#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK) +/* CLK_MISC0_TOG Bit Fields */ +#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK 0x1Fu +#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT 0 +#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_MASK 0x20u +#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_SHIFT 5 +#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_MASK 0x40u +#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_SHIFT 6 +#define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_MASK 0x80u +#define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_SHIFT 7 +#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK 0xFFFFFF00u +#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT 8 +#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK) + +/* REG_1P0A Bit Fields */ +#define PMU_REG_1P0A_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0A_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0A_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0A_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0A_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0A_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0A_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0A_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0A_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0A_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0A_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_BO_OFFSET_SHIFT))&PMU_REG_1P0A_BO_OFFSET_MASK) +#define PMU_REG_1P0A_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0A_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0A_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0A_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0A_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_OUTPUT_TRG_MASK) +#define PMU_REG_1P0A_RSVD0_MASK 0xE000u +#define PMU_REG_1P0A_RSVD0_SHIFT 13 +#define PMU_REG_1P0A_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD0_SHIFT))&PMU_REG_1P0A_RSVD0_MASK) +#define PMU_REG_1P0A_BO_MASK 0x10000u +#define PMU_REG_1P0A_BO_SHIFT 16 +#define PMU_REG_1P0A_OK_MASK 0x20000u +#define PMU_REG_1P0A_OK_SHIFT 17 +#define PMU_REG_1P0A_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0A_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0A_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0A_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0A_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0A_REG_TEST_SHIFT 20 +#define PMU_REG_1P0A_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_REG_TEST_SHIFT))&PMU_REG_1P0A_REG_TEST_MASK) +#define PMU_REG_1P0A_RSVD1_MASK 0xFF000000u +#define PMU_REG_1P0A_RSVD1_SHIFT 24 +#define PMU_REG_1P0A_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD1_SHIFT))&PMU_REG_1P0A_RSVD1_MASK) +/* REG_1P0A_SET Bit Fields */ +#define PMU_REG_1P0A_SET_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0A_SET_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0A_SET_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0A_SET_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0A_SET_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0A_SET_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0A_SET_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0A_SET_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0A_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0A_SET_BO_OFFSET_MASK) +#define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0A_SET_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0A_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_SET_OUTPUT_TRG_MASK) +#define PMU_REG_1P0A_SET_RSVD0_MASK 0xE000u +#define PMU_REG_1P0A_SET_RSVD0_SHIFT 13 +#define PMU_REG_1P0A_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD0_SHIFT))&PMU_REG_1P0A_SET_RSVD0_MASK) +#define PMU_REG_1P0A_SET_BO_MASK 0x10000u +#define PMU_REG_1P0A_SET_BO_SHIFT 16 +#define PMU_REG_1P0A_SET_OK_MASK 0x20000u +#define PMU_REG_1P0A_SET_OK_SHIFT 17 +#define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0A_SET_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0A_SET_REG_TEST_SHIFT 20 +#define PMU_REG_1P0A_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_REG_TEST_SHIFT))&PMU_REG_1P0A_SET_REG_TEST_MASK) +#define PMU_REG_1P0A_SET_RSVD1_MASK 0xFF000000u +#define PMU_REG_1P0A_SET_RSVD1_SHIFT 24 +#define PMU_REG_1P0A_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD1_SHIFT))&PMU_REG_1P0A_SET_RSVD1_MASK) +/* REG_1P0A_CLR Bit Fields */ +#define PMU_REG_1P0A_CLR_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0A_CLR_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0A_CLR_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0A_CLR_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0A_CLR_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0A_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0A_CLR_BO_OFFSET_MASK) +#define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0A_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_1P0A_CLR_RSVD0_MASK 0xE000u +#define PMU_REG_1P0A_CLR_RSVD0_SHIFT 13 +#define PMU_REG_1P0A_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD0_SHIFT))&PMU_REG_1P0A_CLR_RSVD0_MASK) +#define PMU_REG_1P0A_CLR_BO_MASK 0x10000u +#define PMU_REG_1P0A_CLR_BO_SHIFT 16 +#define PMU_REG_1P0A_CLR_OK_MASK 0x20000u +#define PMU_REG_1P0A_CLR_OK_SHIFT 17 +#define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0A_CLR_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0A_CLR_REG_TEST_SHIFT 20 +#define PMU_REG_1P0A_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_REG_TEST_SHIFT))&PMU_REG_1P0A_CLR_REG_TEST_MASK) +#define PMU_REG_1P0A_CLR_RSVD1_MASK 0xFF000000u +#define PMU_REG_1P0A_CLR_RSVD1_SHIFT 24 +#define PMU_REG_1P0A_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD1_SHIFT))&PMU_REG_1P0A_CLR_RSVD1_MASK) +/* REG_1P0A_TOG Bit Fields */ +#define PMU_REG_1P0A_TOG_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0A_TOG_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0A_TOG_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0A_TOG_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0A_TOG_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0A_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0A_TOG_BO_OFFSET_MASK) +#define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0A_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_1P0A_TOG_RSVD0_MASK 0xE000u +#define PMU_REG_1P0A_TOG_RSVD0_SHIFT 13 +#define PMU_REG_1P0A_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD0_SHIFT))&PMU_REG_1P0A_TOG_RSVD0_MASK) +#define PMU_REG_1P0A_TOG_BO_MASK 0x10000u +#define PMU_REG_1P0A_TOG_BO_SHIFT 16 +#define PMU_REG_1P0A_TOG_OK_MASK 0x20000u +#define PMU_REG_1P0A_TOG_OK_SHIFT 17 +#define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0A_TOG_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0A_TOG_REG_TEST_SHIFT 20 +#define PMU_REG_1P0A_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_REG_TEST_SHIFT))&PMU_REG_1P0A_TOG_REG_TEST_MASK) +#define PMU_REG_1P0A_TOG_RSVD1_MASK 0xFF000000u +#define PMU_REG_1P0A_TOG_RSVD1_SHIFT 24 +#define PMU_REG_1P0A_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD1_SHIFT))&PMU_REG_1P0A_TOG_RSVD1_MASK) +/* REG_1P0D Bit Fields */ +#define PMU_REG_1P0D_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0D_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0D_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0D_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0D_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0D_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0D_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0D_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0D_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0D_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0D_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_BO_OFFSET_SHIFT))&PMU_REG_1P0D_BO_OFFSET_MASK) +#define PMU_REG_1P0D_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0D_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0D_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0D_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0D_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_OUTPUT_TRG_MASK) +#define PMU_REG_1P0D_RSVD0_MASK 0xE000u +#define PMU_REG_1P0D_RSVD0_SHIFT 13 +#define PMU_REG_1P0D_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD0_SHIFT))&PMU_REG_1P0D_RSVD0_MASK) +#define PMU_REG_1P0D_BO_MASK 0x10000u +#define PMU_REG_1P0D_BO_SHIFT 16 +#define PMU_REG_1P0D_OK_MASK 0x20000u +#define PMU_REG_1P0D_OK_SHIFT 17 +#define PMU_REG_1P0D_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0D_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0D_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0D_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0D_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0D_REG_TEST_SHIFT 20 +#define PMU_REG_1P0D_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_REG_TEST_SHIFT))&PMU_REG_1P0D_REG_TEST_MASK) +#define PMU_REG_1P0D_RSVD1_MASK 0x7F000000u +#define PMU_REG_1P0D_RSVD1_SHIFT 24 +#define PMU_REG_1P0D_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD1_SHIFT))&PMU_REG_1P0D_RSVD1_MASK) +#define PMU_REG_1P0D_OVERRIDE_MASK 0x80000000u +#define PMU_REG_1P0D_OVERRIDE_SHIFT 31 +/* REG_1P0D_SET Bit Fields */ +#define PMU_REG_1P0D_SET_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0D_SET_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0D_SET_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0D_SET_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0D_SET_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0D_SET_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0D_SET_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0D_SET_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0D_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0D_SET_BO_OFFSET_MASK) +#define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0D_SET_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0D_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_SET_OUTPUT_TRG_MASK) +#define PMU_REG_1P0D_SET_RSVD0_MASK 0xE000u +#define PMU_REG_1P0D_SET_RSVD0_SHIFT 13 +#define PMU_REG_1P0D_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD0_SHIFT))&PMU_REG_1P0D_SET_RSVD0_MASK) +#define PMU_REG_1P0D_SET_BO_MASK 0x10000u +#define PMU_REG_1P0D_SET_BO_SHIFT 16 +#define PMU_REG_1P0D_SET_OK_MASK 0x20000u +#define PMU_REG_1P0D_SET_OK_SHIFT 17 +#define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0D_SET_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0D_SET_REG_TEST_SHIFT 20 +#define PMU_REG_1P0D_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_REG_TEST_SHIFT))&PMU_REG_1P0D_SET_REG_TEST_MASK) +#define PMU_REG_1P0D_SET_RSVD1_MASK 0x7F000000u +#define PMU_REG_1P0D_SET_RSVD1_SHIFT 24 +#define PMU_REG_1P0D_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD1_SHIFT))&PMU_REG_1P0D_SET_RSVD1_MASK) +#define PMU_REG_1P0D_SET_OVERRIDE_MASK 0x80000000u +#define PMU_REG_1P0D_SET_OVERRIDE_SHIFT 31 +/* REG_1P0D_CLR Bit Fields */ +#define PMU_REG_1P0D_CLR_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0D_CLR_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0D_CLR_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0D_CLR_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0D_CLR_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0D_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0D_CLR_BO_OFFSET_MASK) +#define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0D_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_1P0D_CLR_RSVD0_MASK 0xE000u +#define PMU_REG_1P0D_CLR_RSVD0_SHIFT 13 +#define PMU_REG_1P0D_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD0_SHIFT))&PMU_REG_1P0D_CLR_RSVD0_MASK) +#define PMU_REG_1P0D_CLR_BO_MASK 0x10000u +#define PMU_REG_1P0D_CLR_BO_SHIFT 16 +#define PMU_REG_1P0D_CLR_OK_MASK 0x20000u +#define PMU_REG_1P0D_CLR_OK_SHIFT 17 +#define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0D_CLR_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0D_CLR_REG_TEST_SHIFT 20 +#define PMU_REG_1P0D_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_REG_TEST_SHIFT))&PMU_REG_1P0D_CLR_REG_TEST_MASK) +#define PMU_REG_1P0D_CLR_RSVD1_MASK 0x7F000000u +#define PMU_REG_1P0D_CLR_RSVD1_SHIFT 24 +#define PMU_REG_1P0D_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD1_SHIFT))&PMU_REG_1P0D_CLR_RSVD1_MASK) +#define PMU_REG_1P0D_CLR_OVERRIDE_MASK 0x80000000u +#define PMU_REG_1P0D_CLR_OVERRIDE_SHIFT 31 +/* REG_1P0D_TOG Bit Fields */ +#define PMU_REG_1P0D_TOG_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0D_TOG_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0D_TOG_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0D_TOG_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0D_TOG_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0D_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0D_TOG_BO_OFFSET_MASK) +#define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0D_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_1P0D_TOG_RSVD0_MASK 0xE000u +#define PMU_REG_1P0D_TOG_RSVD0_SHIFT 13 +#define PMU_REG_1P0D_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD0_SHIFT))&PMU_REG_1P0D_TOG_RSVD0_MASK) +#define PMU_REG_1P0D_TOG_BO_MASK 0x10000u +#define PMU_REG_1P0D_TOG_BO_SHIFT 16 +#define PMU_REG_1P0D_TOG_OK_MASK 0x20000u +#define PMU_REG_1P0D_TOG_OK_SHIFT 17 +#define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0D_TOG_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0D_TOG_REG_TEST_SHIFT 20 +#define PMU_REG_1P0D_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_REG_TEST_SHIFT))&PMU_REG_1P0D_TOG_REG_TEST_MASK) +#define PMU_REG_1P0D_TOG_RSVD1_MASK 0x7F000000u +#define PMU_REG_1P0D_TOG_RSVD1_SHIFT 24 +#define PMU_REG_1P0D_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD1_SHIFT))&PMU_REG_1P0D_TOG_RSVD1_MASK) +#define PMU_REG_1P0D_TOG_OVERRIDE_MASK 0x80000000u +#define PMU_REG_1P0D_TOG_OVERRIDE_SHIFT 31 +/* REG_HSIC_1P2 Bit Fields */ +#define PMU_REG_HSIC_1P2_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_HSIC_1P2_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_HSIC_1P2_ENABLE_BO_MASK 0x2u +#define PMU_REG_HSIC_1P2_ENABLE_BO_SHIFT 1 +#define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_HSIC_1P2_BO_OFFSET_MASK 0x70u +#define PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT 4 +#define PMU_REG_HSIC_1P2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_BO_OFFSET_MASK) +#define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_HSIC_1P2_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK) +#define PMU_REG_HSIC_1P2_RSVD0_MASK 0xE000u +#define PMU_REG_HSIC_1P2_RSVD0_SHIFT 13 +#define PMU_REG_HSIC_1P2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_RSVD0_MASK) +#define PMU_REG_HSIC_1P2_BO_MASK 0x10000u +#define PMU_REG_HSIC_1P2_BO_SHIFT 16 +#define PMU_REG_HSIC_1P2_OK_MASK 0x20000u +#define PMU_REG_HSIC_1P2_OK_SHIFT 17 +#define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_HSIC_1P2_REG_TEST_MASK 0xF00000u +#define PMU_REG_HSIC_1P2_REG_TEST_SHIFT 20 +#define PMU_REG_HSIC_1P2_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_REG_TEST_MASK) +#define PMU_REG_HSIC_1P2_RSVD1_MASK 0x7F000000u +#define PMU_REG_HSIC_1P2_RSVD1_SHIFT 24 +#define PMU_REG_HSIC_1P2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_RSVD1_MASK) +#define PMU_REG_HSIC_1P2_OVERRIDE_MASK 0x80000000u +#define PMU_REG_HSIC_1P2_OVERRIDE_SHIFT 31 +/* REG_HSIC_1P2_SET Bit Fields */ +#define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_HSIC_1P2_SET_ENABLE_BO_MASK 0x2u +#define PMU_REG_HSIC_1P2_SET_ENABLE_BO_SHIFT 1 +#define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK 0x70u +#define PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT 4 +#define PMU_REG_HSIC_1P2_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK) +#define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK) +#define PMU_REG_HSIC_1P2_SET_RSVD0_MASK 0xE000u +#define PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT 13 +#define PMU_REG_HSIC_1P2_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD0_MASK) +#define PMU_REG_HSIC_1P2_SET_BO_MASK 0x10000u +#define PMU_REG_HSIC_1P2_SET_BO_SHIFT 16 +#define PMU_REG_HSIC_1P2_SET_OK_MASK 0x20000u +#define PMU_REG_HSIC_1P2_SET_OK_SHIFT 17 +#define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_HSIC_1P2_SET_REG_TEST_MASK 0xF00000u +#define PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT 20 +#define PMU_REG_HSIC_1P2_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_SET_REG_TEST_MASK) +#define PMU_REG_HSIC_1P2_SET_RSVD1_MASK 0x7F000000u +#define PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT 24 +#define PMU_REG_HSIC_1P2_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD1_MASK) +#define PMU_REG_HSIC_1P2_SET_OVERRIDE_MASK 0x80000000u +#define PMU_REG_HSIC_1P2_SET_OVERRIDE_SHIFT 31 +/* REG_HSIC_1P2_CLR Bit Fields */ +#define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_MASK 0x2u +#define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_SHIFT 1 +#define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK 0x70u +#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT 4 +#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK) +#define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_HSIC_1P2_CLR_RSVD0_MASK 0xE000u +#define PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT 13 +#define PMU_REG_HSIC_1P2_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD0_MASK) +#define PMU_REG_HSIC_1P2_CLR_BO_MASK 0x10000u +#define PMU_REG_HSIC_1P2_CLR_BO_SHIFT 16 +#define PMU_REG_HSIC_1P2_CLR_OK_MASK 0x20000u +#define PMU_REG_HSIC_1P2_CLR_OK_SHIFT 17 +#define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK 0xF00000u +#define PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT 20 +#define PMU_REG_HSIC_1P2_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK) +#define PMU_REG_HSIC_1P2_CLR_RSVD1_MASK 0x7F000000u +#define PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT 24 +#define PMU_REG_HSIC_1P2_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD1_MASK) +#define PMU_REG_HSIC_1P2_CLR_OVERRIDE_MASK 0x80000000u +#define PMU_REG_HSIC_1P2_CLR_OVERRIDE_SHIFT 31 +/* REG_HSIC_1P2_TOG Bit Fields */ +#define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_MASK 0x2u +#define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_SHIFT 1 +#define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK 0x70u +#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT 4 +#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK) +#define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_HSIC_1P2_TOG_RSVD0_MASK 0xE000u +#define PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT 13 +#define PMU_REG_HSIC_1P2_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD0_MASK) +#define PMU_REG_HSIC_1P2_TOG_BO_MASK 0x10000u +#define PMU_REG_HSIC_1P2_TOG_BO_SHIFT 16 +#define PMU_REG_HSIC_1P2_TOG_OK_MASK 0x20000u +#define PMU_REG_HSIC_1P2_TOG_OK_SHIFT 17 +#define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK 0xF00000u +#define PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT 20 +#define PMU_REG_HSIC_1P2_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK) +#define PMU_REG_HSIC_1P2_TOG_RSVD1_MASK 0x7F000000u +#define PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT 24 +#define PMU_REG_HSIC_1P2_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD1_MASK) +#define PMU_REG_HSIC_1P2_TOG_OVERRIDE_MASK 0x80000000u +#define PMU_REG_HSIC_1P2_TOG_OVERRIDE_SHIFT 31 +/* REG_LPSR_1P0 Bit Fields */ +#define PMU_REG_LPSR_1P0_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_LPSR_1P0_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_LPSR_1P0_ENABLE_BO_MASK 0x2u +#define PMU_REG_LPSR_1P0_ENABLE_BO_SHIFT 1 +#define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_LPSR_1P0_BO_OFFSET_MASK 0x70u +#define PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT 4 +#define PMU_REG_LPSR_1P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_BO_OFFSET_MASK) +#define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_LPSR_1P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK) +#define PMU_REG_LPSR_1P0_RSVD0_MASK 0xE000u +#define PMU_REG_LPSR_1P0_RSVD0_SHIFT 13 +#define PMU_REG_LPSR_1P0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_RSVD0_MASK) +#define PMU_REG_LPSR_1P0_BO_MASK 0x10000u +#define PMU_REG_LPSR_1P0_BO_SHIFT 16 +#define PMU_REG_LPSR_1P0_OK_MASK 0x20000u +#define PMU_REG_LPSR_1P0_OK_SHIFT 17 +#define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_LPSR_1P0_REG_TEST_MASK 0xF00000u +#define PMU_REG_LPSR_1P0_REG_TEST_SHIFT 20 +#define PMU_REG_LPSR_1P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_REG_TEST_MASK) +#define PMU_REG_LPSR_1P0_RSVD1_MASK 0xFF000000u +#define PMU_REG_LPSR_1P0_RSVD1_SHIFT 24 +#define PMU_REG_LPSR_1P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_RSVD1_MASK) +/* REG_LPSR_1P0_SET Bit Fields */ +#define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_LPSR_1P0_SET_ENABLE_BO_MASK 0x2u +#define PMU_REG_LPSR_1P0_SET_ENABLE_BO_SHIFT 1 +#define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK 0x70u +#define PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT 4 +#define PMU_REG_LPSR_1P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK) +#define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK) +#define PMU_REG_LPSR_1P0_SET_RSVD0_MASK 0xE000u +#define PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT 13 +#define PMU_REG_LPSR_1P0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD0_MASK) +#define PMU_REG_LPSR_1P0_SET_BO_MASK 0x10000u +#define PMU_REG_LPSR_1P0_SET_BO_SHIFT 16 +#define PMU_REG_LPSR_1P0_SET_OK_MASK 0x20000u +#define PMU_REG_LPSR_1P0_SET_OK_SHIFT 17 +#define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_LPSR_1P0_SET_REG_TEST_MASK 0xF00000u +#define PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT 20 +#define PMU_REG_LPSR_1P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_SET_REG_TEST_MASK) +#define PMU_REG_LPSR_1P0_SET_RSVD1_MASK 0xFF000000u +#define PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT 24 +#define PMU_REG_LPSR_1P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD1_MASK) +/* REG_LPSR_1P0_CLR Bit Fields */ +#define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_MASK 0x2u +#define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_SHIFT 1 +#define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK 0x70u +#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT 4 +#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK) +#define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_LPSR_1P0_CLR_RSVD0_MASK 0xE000u +#define PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT 13 +#define PMU_REG_LPSR_1P0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD0_MASK) +#define PMU_REG_LPSR_1P0_CLR_BO_MASK 0x10000u +#define PMU_REG_LPSR_1P0_CLR_BO_SHIFT 16 +#define PMU_REG_LPSR_1P0_CLR_OK_MASK 0x20000u +#define PMU_REG_LPSR_1P0_CLR_OK_SHIFT 17 +#define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK 0xF00000u +#define PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT 20 +#define PMU_REG_LPSR_1P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK) +#define PMU_REG_LPSR_1P0_CLR_RSVD1_MASK 0xFF000000u +#define PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT 24 +#define PMU_REG_LPSR_1P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD1_MASK) +/* REG_LPSR_1P0_TOG Bit Fields */ +#define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_MASK 0x2u +#define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_SHIFT 1 +#define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK 0x70u +#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT 4 +#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK) +#define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_LPSR_1P0_TOG_RSVD0_MASK 0xE000u +#define PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT 13 +#define PMU_REG_LPSR_1P0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD0_MASK) +#define PMU_REG_LPSR_1P0_TOG_BO_MASK 0x10000u +#define PMU_REG_LPSR_1P0_TOG_BO_SHIFT 16 +#define PMU_REG_LPSR_1P0_TOG_OK_MASK 0x20000u +#define PMU_REG_LPSR_1P0_TOG_OK_SHIFT 17 +#define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK 0xF00000u +#define PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT 20 +#define PMU_REG_LPSR_1P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK) +#define PMU_REG_LPSR_1P0_TOG_RSVD1_MASK 0xFF000000u +#define PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT 24 +#define PMU_REG_LPSR_1P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD1_MASK) +/* REG_3P0 Bit Fields */ +#define PMU_REG_3P0_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_3P0_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_3P0_ENABLE_BO_MASK 0x2u +#define PMU_REG_3P0_ENABLE_BO_SHIFT 1 +#define PMU_REG_3P0_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_3P0_RSVD0_MASK 0x8u +#define PMU_REG_3P0_RSVD0_SHIFT 3 +#define PMU_REG_3P0_BO_OFFSET_MASK 0x70u +#define PMU_REG_3P0_BO_OFFSET_SHIFT 4 +#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_BO_OFFSET_SHIFT))&PMU_REG_3P0_BO_OFFSET_MASK) +#define PMU_REG_3P0_VBUS_SEL_MASK 0x80u +#define PMU_REG_3P0_VBUS_SEL_SHIFT 7 +#define PMU_REG_3P0_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_3P0_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_RSVD1_MASK 0xE000u +#define PMU_REG_3P0_RSVD1_SHIFT 13 +#define PMU_REG_3P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD1_SHIFT))&PMU_REG_3P0_RSVD1_MASK) +#define PMU_REG_3P0_BO_VDD3P0_MASK 0x10000u +#define PMU_REG_3P0_BO_VDD3P0_SHIFT 16 +#define PMU_REG_3P0_OK_VDD3P0_MASK 0x20000u +#define PMU_REG_3P0_OK_VDD3P0_SHIFT 17 +#define PMU_REG_3P0_REG_TEST_MASK 0x3C0000u +#define PMU_REG_3P0_REG_TEST_SHIFT 18 +#define PMU_REG_3P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_REG_TEST_SHIFT))&PMU_REG_3P0_REG_TEST_MASK) +#define PMU_REG_3P0_RSVD2_MASK 0xFFC00000u +#define PMU_REG_3P0_RSVD2_SHIFT 22 +#define PMU_REG_3P0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD2_SHIFT))&PMU_REG_3P0_RSVD2_MASK) +/* REG_3P0_SET Bit Fields */ +#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_3P0_SET_ENABLE_BO_MASK 0x2u +#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT 1 +#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_3P0_SET_RSVD0_MASK 0x8u +#define PMU_REG_3P0_SET_RSVD0_SHIFT 3 +#define PMU_REG_3P0_SET_BO_OFFSET_MASK 0x70u +#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT 4 +#define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_BO_OFFSET_SHIFT))&PMU_REG_3P0_SET_BO_OFFSET_MASK) +#define PMU_REG_3P0_SET_VBUS_SEL_MASK 0x80u +#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT 7 +#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_SET_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_SET_RSVD1_MASK 0xE000u +#define PMU_REG_3P0_SET_RSVD1_SHIFT 13 +#define PMU_REG_3P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD1_SHIFT))&PMU_REG_3P0_SET_RSVD1_MASK) +#define PMU_REG_3P0_SET_BO_VDD3P0_MASK 0x10000u +#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT 16 +#define PMU_REG_3P0_SET_OK_VDD3P0_MASK 0x20000u +#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT 17 +#define PMU_REG_3P0_SET_REG_TEST_MASK 0x3C0000u +#define PMU_REG_3P0_SET_REG_TEST_SHIFT 18 +#define PMU_REG_3P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_REG_TEST_SHIFT))&PMU_REG_3P0_SET_REG_TEST_MASK) +#define PMU_REG_3P0_SET_RSVD2_MASK 0xFFC00000u +#define PMU_REG_3P0_SET_RSVD2_SHIFT 22 +#define PMU_REG_3P0_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD2_SHIFT))&PMU_REG_3P0_SET_RSVD2_MASK) +/* REG_3P0_CLR Bit Fields */ +#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_3P0_CLR_ENABLE_BO_MASK 0x2u +#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT 1 +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_3P0_CLR_RSVD0_MASK 0x8u +#define PMU_REG_3P0_CLR_RSVD0_SHIFT 3 +#define PMU_REG_3P0_CLR_BO_OFFSET_MASK 0x70u +#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT 4 +#define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_3P0_CLR_BO_OFFSET_MASK) +#define PMU_REG_3P0_CLR_VBUS_SEL_MASK 0x80u +#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT 7 +#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_CLR_RSVD1_MASK 0xE000u +#define PMU_REG_3P0_CLR_RSVD1_SHIFT 13 +#define PMU_REG_3P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD1_SHIFT))&PMU_REG_3P0_CLR_RSVD1_MASK) +#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK 0x10000u +#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT 16 +#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK 0x20000u +#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT 17 +#define PMU_REG_3P0_CLR_REG_TEST_MASK 0x3C0000u +#define PMU_REG_3P0_CLR_REG_TEST_SHIFT 18 +#define PMU_REG_3P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_REG_TEST_SHIFT))&PMU_REG_3P0_CLR_REG_TEST_MASK) +#define PMU_REG_3P0_CLR_RSVD2_MASK 0xFFC00000u +#define PMU_REG_3P0_CLR_RSVD2_SHIFT 22 +#define PMU_REG_3P0_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD2_SHIFT))&PMU_REG_3P0_CLR_RSVD2_MASK) +/* REG_3P0_TOG Bit Fields */ +#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_3P0_TOG_ENABLE_BO_MASK 0x2u +#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT 1 +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_3P0_TOG_RSVD0_MASK 0x8u +#define PMU_REG_3P0_TOG_RSVD0_SHIFT 3 +#define PMU_REG_3P0_TOG_BO_OFFSET_MASK 0x70u +#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT 4 +#define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_3P0_TOG_BO_OFFSET_MASK) +#define PMU_REG_3P0_TOG_VBUS_SEL_MASK 0x80u +#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT 7 +#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_TOG_RSVD1_MASK 0xE000u +#define PMU_REG_3P0_TOG_RSVD1_SHIFT 13 +#define PMU_REG_3P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD1_SHIFT))&PMU_REG_3P0_TOG_RSVD1_MASK) +#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK 0x10000u +#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT 16 +#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK 0x20000u +#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT 17 +#define PMU_REG_3P0_TOG_REG_TEST_MASK 0x3C0000u +#define PMU_REG_3P0_TOG_REG_TEST_SHIFT 18 +#define PMU_REG_3P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_REG_TEST_SHIFT))&PMU_REG_3P0_TOG_REG_TEST_MASK) +#define PMU_REG_3P0_TOG_RSVD2_MASK 0xFFC00000u +#define PMU_REG_3P0_TOG_RSVD2_SHIFT 22 +#define PMU_REG_3P0_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD2_SHIFT))&PMU_REG_3P0_TOG_RSVD2_MASK) +/* REF Bit Fields */ +#define PMU_REF_REFTOP_PWD_MASK 0x1u +#define PMU_REF_REFTOP_PWD_SHIFT 0 +#define PMU_REF_REFTOP_PWDVBGUP_MASK 0x2u +#define PMU_REF_REFTOP_PWDVBGUP_SHIFT 1 +#define PMU_REF_REFTOP_LOWPOWER_MASK 0x4u +#define PMU_REF_REFTOP_LOWPOWER_SHIFT 2 +#define PMU_REF_REFTOP_SELFBIASOFF_MASK 0x8u +#define PMU_REF_REFTOP_SELFBIASOFF_SHIFT 3 +#define PMU_REF_REFTOP_VBGADJ_MASK 0x70u +#define PMU_REF_REFTOP_VBGADJ_SHIFT 4 +#define PMU_REF_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_VBGADJ_SHIFT))&PMU_REF_REFTOP_VBGADJ_MASK) +#define PMU_REF_REFTOP_VBGUP_MASK 0x80u +#define PMU_REF_REFTOP_VBGUP_SHIFT 7 +#define PMU_REF_REFTOP_BIAS_TST_MASK 0x300u +#define PMU_REF_REFTOP_BIAS_TST_SHIFT 8 +#define PMU_REF_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_BIAS_TST_SHIFT))&PMU_REF_REFTOP_BIAS_TST_MASK) +#define PMU_REF_LPBG_SEL_MASK 0x400u +#define PMU_REF_LPBG_SEL_SHIFT 10 +#define PMU_REF_LPBG_TEST_MASK 0x800u +#define PMU_REF_LPBG_TEST_SHIFT 11 +#define PMU_REF_REFTOP_IBIAS_OFF_MASK 0x1000u +#define PMU_REF_REFTOP_IBIAS_OFF_SHIFT 12 +#define PMU_REF_REFTOP_LINREGREF_EN_MASK 0x2000u +#define PMU_REF_REFTOP_LINREGREF_EN_SHIFT 13 +#define PMU_REF_RSVD1_MASK 0xFFFFC000u +#define PMU_REF_RSVD1_SHIFT 14 +#define PMU_REF_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_RSVD1_SHIFT))&PMU_REF_RSVD1_MASK) +/* REF_SET Bit Fields */ +#define PMU_REF_SET_REFTOP_PWD_MASK 0x1u +#define PMU_REF_SET_REFTOP_PWD_SHIFT 0 +#define PMU_REF_SET_REFTOP_PWDVBGUP_MASK 0x2u +#define PMU_REF_SET_REFTOP_PWDVBGUP_SHIFT 1 +#define PMU_REF_SET_REFTOP_LOWPOWER_MASK 0x4u +#define PMU_REF_SET_REFTOP_LOWPOWER_SHIFT 2 +#define PMU_REF_SET_REFTOP_SELFBIASOFF_MASK 0x8u +#define PMU_REF_SET_REFTOP_SELFBIASOFF_SHIFT 3 +#define PMU_REF_SET_REFTOP_VBGADJ_MASK 0x70u +#define PMU_REF_SET_REFTOP_VBGADJ_SHIFT 4 +#define PMU_REF_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_VBGADJ_SHIFT))&PMU_REF_SET_REFTOP_VBGADJ_MASK) +#define PMU_REF_SET_REFTOP_VBGUP_MASK 0x80u +#define PMU_REF_SET_REFTOP_VBGUP_SHIFT 7 +#define PMU_REF_SET_REFTOP_BIAS_TST_MASK 0x300u +#define PMU_REF_SET_REFTOP_BIAS_TST_SHIFT 8 +#define PMU_REF_SET_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_BIAS_TST_SHIFT))&PMU_REF_SET_REFTOP_BIAS_TST_MASK) +#define PMU_REF_SET_LPBG_SEL_MASK 0x400u +#define PMU_REF_SET_LPBG_SEL_SHIFT 10 +#define PMU_REF_SET_LPBG_TEST_MASK 0x800u +#define PMU_REF_SET_LPBG_TEST_SHIFT 11 +#define PMU_REF_SET_REFTOP_IBIAS_OFF_MASK 0x1000u +#define PMU_REF_SET_REFTOP_IBIAS_OFF_SHIFT 12 +#define PMU_REF_SET_REFTOP_LINREGREF_EN_MASK 0x2000u +#define PMU_REF_SET_REFTOP_LINREGREF_EN_SHIFT 13 +#define PMU_REF_SET_RSVD1_MASK 0xFFFFC000u +#define PMU_REF_SET_RSVD1_SHIFT 14 +#define PMU_REF_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_RSVD1_SHIFT))&PMU_REF_SET_RSVD1_MASK) +/* REF_CLR Bit Fields */ +#define PMU_REF_CLR_REFTOP_PWD_MASK 0x1u +#define PMU_REF_CLR_REFTOP_PWD_SHIFT 0 +#define PMU_REF_CLR_REFTOP_PWDVBGUP_MASK 0x2u +#define PMU_REF_CLR_REFTOP_PWDVBGUP_SHIFT 1 +#define PMU_REF_CLR_REFTOP_LOWPOWER_MASK 0x4u +#define PMU_REF_CLR_REFTOP_LOWPOWER_SHIFT 2 +#define PMU_REF_CLR_REFTOP_SELFBIASOFF_MASK 0x8u +#define PMU_REF_CLR_REFTOP_SELFBIASOFF_SHIFT 3 +#define PMU_REF_CLR_REFTOP_VBGADJ_MASK 0x70u +#define PMU_REF_CLR_REFTOP_VBGADJ_SHIFT 4 +#define PMU_REF_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_VBGADJ_SHIFT))&PMU_REF_CLR_REFTOP_VBGADJ_MASK) +#define PMU_REF_CLR_REFTOP_VBGUP_MASK 0x80u +#define PMU_REF_CLR_REFTOP_VBGUP_SHIFT 7 +#define PMU_REF_CLR_REFTOP_BIAS_TST_MASK 0x300u +#define PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT 8 +#define PMU_REF_CLR_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT))&PMU_REF_CLR_REFTOP_BIAS_TST_MASK) +#define PMU_REF_CLR_LPBG_SEL_MASK 0x400u +#define PMU_REF_CLR_LPBG_SEL_SHIFT 10 +#define PMU_REF_CLR_LPBG_TEST_MASK 0x800u +#define PMU_REF_CLR_LPBG_TEST_SHIFT 11 +#define PMU_REF_CLR_REFTOP_IBIAS_OFF_MASK 0x1000u +#define PMU_REF_CLR_REFTOP_IBIAS_OFF_SHIFT 12 +#define PMU_REF_CLR_REFTOP_LINREGREF_EN_MASK 0x2000u +#define PMU_REF_CLR_REFTOP_LINREGREF_EN_SHIFT 13 +#define PMU_REF_CLR_RSVD1_MASK 0xFFFFC000u +#define PMU_REF_CLR_RSVD1_SHIFT 14 +#define PMU_REF_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_RSVD1_SHIFT))&PMU_REF_CLR_RSVD1_MASK) +/* REF_TOG Bit Fields */ +#define PMU_REF_TOG_REFTOP_PWD_MASK 0x1u +#define PMU_REF_TOG_REFTOP_PWD_SHIFT 0 +#define PMU_REF_TOG_REFTOP_PWDVBGUP_MASK 0x2u +#define PMU_REF_TOG_REFTOP_PWDVBGUP_SHIFT 1 +#define PMU_REF_TOG_REFTOP_LOWPOWER_MASK 0x4u +#define PMU_REF_TOG_REFTOP_LOWPOWER_SHIFT 2 +#define PMU_REF_TOG_REFTOP_SELFBIASOFF_MASK 0x8u +#define PMU_REF_TOG_REFTOP_SELFBIASOFF_SHIFT 3 +#define PMU_REF_TOG_REFTOP_VBGADJ_MASK 0x70u +#define PMU_REF_TOG_REFTOP_VBGADJ_SHIFT 4 +#define PMU_REF_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_VBGADJ_SHIFT))&PMU_REF_TOG_REFTOP_VBGADJ_MASK) +#define PMU_REF_TOG_REFTOP_VBGUP_MASK 0x80u +#define PMU_REF_TOG_REFTOP_VBGUP_SHIFT 7 +#define PMU_REF_TOG_REFTOP_BIAS_TST_MASK 0x300u +#define PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT 8 +#define PMU_REF_TOG_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT))&PMU_REF_TOG_REFTOP_BIAS_TST_MASK) +#define PMU_REF_TOG_LPBG_SEL_MASK 0x400u +#define PMU_REF_TOG_LPBG_SEL_SHIFT 10 +#define PMU_REF_TOG_LPBG_TEST_MASK 0x800u +#define PMU_REF_TOG_LPBG_TEST_SHIFT 11 +#define PMU_REF_TOG_REFTOP_IBIAS_OFF_MASK 0x1000u +#define PMU_REF_TOG_REFTOP_IBIAS_OFF_SHIFT 12 +#define PMU_REF_TOG_REFTOP_LINREGREF_EN_MASK 0x2000u +#define PMU_REF_TOG_REFTOP_LINREGREF_EN_SHIFT 13 +#define PMU_REF_TOG_RSVD1_MASK 0xFFFFC000u +#define PMU_REF_TOG_RSVD1_SHIFT 14 +#define PMU_REF_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_RSVD1_SHIFT))&PMU_REF_TOG_RSVD1_MASK) +/* LOWPWR_CTRL Bit Fields */ +#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK 0x3u +#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT 0 +#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK) +#define PMU_LOWPWR_CTRL_RSVD0_MASK 0xFCu +#define PMU_LOWPWR_CTRL_RSVD0_SHIFT 2 +#define PMU_LOWPWR_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_RSVD0_MASK) +#define PMU_LOWPWR_CTRL_L1_PWRGATE_MASK 0x100u +#define PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT 8 +#define PMU_LOWPWR_CTRL_L2_PWRGATE_MASK 0x200u +#define PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT 9 +#define PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK 0x400u +#define PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT 10 +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK 0x800u +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT 11 +#define PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK 0x1000u +#define PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT 12 +#define PMU_LOWPWR_CTRL_GPU_PWRGATE_MASK 0x2000u +#define PMU_LOWPWR_CTRL_GPU_PWRGATE_SHIFT 13 +#define PMU_LOWPWR_CTRL_CONTROL0_MASK 0xFFC000u +#define PMU_LOWPWR_CTRL_CONTROL0_SHIFT 14 +#define PMU_LOWPWR_CTRL_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CONTROL0_MASK) +#define PMU_LOWPWR_CTRL_CONTROL1_MASK 0xFF000000u +#define PMU_LOWPWR_CTRL_CONTROL1_SHIFT 24 +#define PMU_LOWPWR_CTRL_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CONTROL1_MASK) +/* LOWPWR_CTRL_SET Bit Fields */ +#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK 0x3u +#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT 0 +#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK) +#define PMU_LOWPWR_CTRL_SET_RSVD0_MASK 0xFCu +#define PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT 2 +#define PMU_LOWPWR_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_SET_RSVD0_MASK) +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK 0x100u +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT 8 +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK 0x200u +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT 9 +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK 0x400u +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT 10 +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK 0x800u +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT 11 +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK 0x1000u +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT 12 +#define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK 0x2000u +#define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT 13 +#define PMU_LOWPWR_CTRL_SET_CONTROL0_MASK 0xFFC000u +#define PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT 14 +#define PMU_LOWPWR_CTRL_SET_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL0_MASK) +#define PMU_LOWPWR_CTRL_SET_CONTROL1_MASK 0xFF000000u +#define PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT 24 +#define PMU_LOWPWR_CTRL_SET_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL1_MASK) +/* LOWPWR_CTRL_CLR Bit Fields */ +#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK 0x3u +#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT 0 +#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK) +#define PMU_LOWPWR_CTRL_CLR_RSVD0_MASK 0xFCu +#define PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT 2 +#define PMU_LOWPWR_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_CLR_RSVD0_MASK) +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK 0x100u +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT 8 +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK 0x200u +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT 9 +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK 0x400u +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT 10 +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK 0x800u +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT 11 +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK 0x1000u +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT 12 +#define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK 0x2000u +#define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT 13 +#define PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK 0xFFC000u +#define PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT 14 +#define PMU_LOWPWR_CTRL_CLR_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK) +#define PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK 0xFF000000u +#define PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT 24 +#define PMU_LOWPWR_CTRL_CLR_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK) +/* LOWPWR_CTRL_TOG Bit Fields */ +#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK 0x3u +#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT 0 +#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK) +#define PMU_LOWPWR_CTRL_TOG_RSVD0_MASK 0xFCu +#define PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT 2 +#define PMU_LOWPWR_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_TOG_RSVD0_MASK) +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK 0x100u +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT 8 +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK 0x200u +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT 9 +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK 0x400u +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT 10 +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK 0x800u +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT 11 +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK 0x1000u +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT 12 +#define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK 0x2000u +#define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT 13 +#define PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK 0xFFC000u +#define PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT 14 +#define PMU_LOWPWR_CTRL_TOG_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK) +#define PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK 0xFF000000u +#define PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT 24 +#define PMU_LOWPWR_CTRL_TOG_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK) + + +/* HW_ANADIG_TEMPSENSE0 Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK 0x3FE00u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK 0x7FC0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT 18 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK 0xF8000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT 27 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK) +/* HW_ANADIG_TEMPSENSE0_SET Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK 0x3FE00u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK 0x7FC0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT 18 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK 0xF8000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT 27 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK) +/* HW_ANADIG_TEMPSENSE0_CLR Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK 0x3FE00u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK 0x7FC0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT 18 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK 0xF8000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT 27 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK) +/* HW_ANADIG_TEMPSENSE0_TOG Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK 0x3FE00u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK 0x7FC0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT 18 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK 0xF8000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT 27 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK) +/* HW_ANADIG_TEMPSENSE1 Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK 0x200u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK 0x400u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_SHIFT 10 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK 0x800u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_SHIFT 11 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK 0xF000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT 12 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK 0xFFFF0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT 16 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK) +/* HW_ANADIG_TEMPSENSE1_SET Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_MASK 0x200u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_MASK 0x400u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_SHIFT 10 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_MASK 0x800u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_SHIFT 11 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK 0xF000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT 12 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK 0xFFFF0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT 16 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK) +/* HW_ANADIG_TEMPSENSE1_CLR Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_MASK 0x200u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_MASK 0x400u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_SHIFT 10 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_MASK 0x800u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_SHIFT 11 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK 0xF000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT 12 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK 0xFFFF0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT 16 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) +/* HW_ANADIG_TEMPSENSE1_TOG Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_MASK 0x200u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_MASK 0x400u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_SHIFT 10 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_MASK 0x800u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_SHIFT 11 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK 0xF000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT 12 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK 0xFFFF0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT 16 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) +/* HW_ANADIG_TEMPSENSE_TRIM Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK 0x1Fu +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK 0x60u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT 5 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_MASK 0x80u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_SHIFT 7 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK 0x1FF00u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT 8 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK 0xE0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT 17 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK 0xF00000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT 20 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK 0x1F000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT 24 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK 0xE0000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT 29 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK) +/* HW_ANADIG_TEMPSENSE_TRIM_SET Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK 0x1Fu +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK 0x60u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT 5 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_MASK 0x80u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_SHIFT 7 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK 0x1FF00u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT 8 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK 0xE0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT 17 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK 0xF00000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT 20 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK 0x1F000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT 24 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK 0xE0000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT 29 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK) +/* HW_ANADIG_TEMPSENSE_TRIM_CLR Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK 0x1Fu +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK 0x60u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT 5 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_MASK 0x80u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_SHIFT 7 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK 0x1FF00u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT 8 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK 0xE0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT 17 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK 0xF00000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT 20 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK 0x1F000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT 24 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK 0xE0000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT 29 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK) +/* HW_ANADIG_TEMPSENSE_TRIM_TOG Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK 0x1Fu +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK 0x60u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT 5 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_MASK 0x80u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_SHIFT 7 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK 0x1FF00u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT 8 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK 0xE0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT 17 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK 0xF00000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT 20 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK 0x1F000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT 24 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK 0xE0000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK) + + +#define CCM_GPR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i)) +#define CCM_OBSERVE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i)) +#define CCM_SCTRL(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i)) +#define CCM_CCGR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i)) +#define CCM_ROOT_TARGET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i)) + +#define CCM_GPR_SET(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 4) +#define CCM_OBSERVE_SET(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4) +#define CCM_SCTRL_SET(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4) +#define CCM_CCGR_SET(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 4) +#define CCM_ROOT_TARGET_SET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4) + +#define CCM_GPR_CLR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 8) +#define CCM_OBSERVE_CLR(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8) +#define CCM_SCTRL_CLR(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8) +#define CCM_CCGR_CLR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 8) +#define CCM_ROOT_TARGET_CLR(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8) + +#define CCM_GPR_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 12) +#define CCM_OBSERVE_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12) +#define CCM_SCTRL_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12) +#define CCM_CCGR_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 12) +#define CCM_ROOT_TARGET_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12) + +#define HW_CCM_GPR_WR(i, v) writel((v), CCM_GPR(i)) +#define HW_CCM_CCM_OBSERVE_WR(i, v) writel((v), CCM_OBSERVE(i)) +#define HW_CCM_SCTRL_WR(i, v) writel((v), CCM_SCTRL(i)) +#define HW_CCM_CCGR_WR(i, v) writel((v), CCM_CCGR(i)) +#define HW_CCM_ROOT_TARGET_WR(i, v) writel((v), CCM_ROOT_TARGET(i)) + +#define HW_CCM_GPR_RD(i) readl(CCM_GPR(i)) +#define HW_CCM_CCM_OBSERVE_RD(i) readl(CCM_OBSERVE(i)) +#define HW_CCM_SCTRL_RD(i) readl(CCM_SCTRL(i)) +#define HW_CCM_CCGR_RD(i) readl(CCM_CCGR(i)) +#define HW_CCM_ROOT_TARGET_RD(i) readl(CCM_ROOT_TARGET(i)) + +#define HW_CCM_GPR_SET(i, v) writel((v), CCM_GPR_SET(i)) +#define HW_CCM_CCM_OBSERVE_SET(i, v) writel((v), CCM_CCM_OBSERVE_SET(i)) +#define HW_CCM_SCTRL_SET(i, v) writel((v), CCM_SCTRL_SET(i)) +#define HW_CCM_CCGR_SET(i, v) writel((v), CCM_CCGR_SET(i)) +#define HW_CCM_ROOT_TARGET_SET(i, v) writel((v), CCM_ROOT_TARGET_SET(i)) + +#define HW_CCM_GPR_CLR(i, v) writel((v), CCM_GPR_CLR(i)) +#define HW_CCM_CCM_OBSERVE_CLR(i, v) writel((v), CCM_CCM_OBSERVE_CLR(i)) +#define HW_CCM_SCTRL_CLR(i, v) writel((v), CCM_SCTRL_CLR(i)) +#define HW_CCM_CCGR_CLR(i, v) writel((v), CCM_CCGR_CLR(i)) +#define HW_CCM_ROOT_TARGET_CLR(i, v) writel((v), CCM_ROOT_TARGET_CLR(i)) + +#define HW_CCM_GPR_TOGGLE(i, v) writel((v), CCM_GPR_TOGGLE(i)) +#define HW_CCM_CCM_OBSERVE_TOGGLE(i, v) writel((v), CCM_CCM_OBSERVE_TOGGLE(i)) +#define HW_CCM_SCTRL_TOGGLE(i, v) writel((v), CCM_SCTRL_TOGGLE(i)) +#define HW_CCM_CCGR_TOGGLE(i, v) writel((v), CCM_CCGR_TOGGLE(i)) +#define HW_CCM_ROOT_TARGET_TOGGLE(i, v) writel((v), CCM_ROOT_TARGET_TOGGLE(i)) + +#define CCM_CLK_ON_MSK 0x03 + +#define CCM_ROOT_TGT_POST_DIV_SHIFT 0 +#define CCM_ROOT_TGT_PRE_DIV_SHIFT 15 +#define CCM_ROOT_TGT_MUX_SHIFT 24 +#define CCM_ROOT_TGT_ENABLE_SHIFT 28 +#define CCM_ROOT_TGT_POST_DIV_MSK 0x3F +#define CCM_ROOT_TGT_PRE_DIV_MSK (0x07 << CCM_ROOT_TGT_PRE_DIV_SHIFT) +#define CCM_ROOT_TGT_MUX_MSK (0x07 << CCM_ROOT_TGT_MUX_SHIFT) +#define CCM_ROOT_TGT_ENABLE_MSK (0x01 << CCM_ROOT_TGT_ENABLE_SHIFT) + +#define CCM_ROOT_TGT_POST_DIV(x) ((((x) - 1) << CCM_ROOT_TGT_POST_DIV_SHIFT) & CCM_ROOT_TGT_POST_DIV_MSK) +#define CCM_ROOT_TGT_PRE_DIV(x) ((((x) - 1) << CCM_ROOT_TGT_PRE_DIV_SHIFT) & CCM_ROOT_TGT_PRE_DIV_MSK) +#define CCM_ROOT_TGT_MUX_TO(x) ((((x) - 1) << CCM_ROOT_TGT_MUX_SHIFT) & CCM_ROOT_TGT_MUX_MSK) + +/* + * Field values definition for clock slice TARGET register + */ + +#define CLK_ROOT_ON 0x10000000 +#define CLK_ROOT_OFF 0x0 +#define CLK_ROOT_ENABLE_MASK 0x10000000 +#define CLK_ROOT_ENABLE_SHIFT 28 + +#define CLK_ROOT_ALT0 0x00000000 +#define CLK_ROOT_ALT1 0x01000000 +#define CLK_ROOT_ALT2 0x02000000 +#define CLK_ROOT_ALT3 0x03000000 +#define CLK_ROOT_ALT4 0x04000000 +#define CLK_ROOT_ALT5 0x05000000 +#define CLK_ROOT_ALT6 0x06000000 +#define CLK_ROOT_ALT7 0x07000000 + + +#define DRAM_CLK_ROOT_POST_DIV_MASK 0x00000007 +#define CLK_ROOT_POST_DIV_MASK 0x0000003f +#define CLK_ROOT_POST_DIV_SHIFT 0 +#define CLK_ROOT_POST_DIV(n) ((n << CLK_ROOT_POST_DIV_SHIFT) & CLK_ROOT_POST_DIV_MASK) + +#define CLK_ROOT_AUTO_DIV_MASK 0x00000700 +#define CLK_ROOT_AUTO_DIV_SHIFT 8 +#define CLK_ROOT_AUTO_DIV(n) ((n << CLK_ROOT_AUTO_DIV_SHIFT) & CLK_ROOT_AUTO_DIV_MASK) + +#define CLK_ROOT_AUTO_EN_MASK 0x00001000 +#define CLK_ROOT_AUTO_EN 0x00001000 + +#define CLK_ROOT_PRE_DIV_MASK 0x00070000 +#define CLK_ROOT_PRE_DIV_SHIFT 16 +#define CLK_ROOT_PRE_DIV(n) ((n << CLK_ROOT_PRE_DIV_SHIFT) & CLK_ROOT_PRE_DIV_MASK) + +#define CLK_ROOT_MUX_MASK 0x07000000 +#define CLK_ROOT_MUX_SHIFT 24 + +#define CLK_ROOT_EN_MASK 0x10000000 + +#define CLK_ROOT_AUTO_ON 0x00001000 +#define CLK_ROOT_AUTO_OFF 0x0 + +/* ARM_A7_CLK_ROOT */ +#define ARM_A7_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ARM_A7_CLK_ROOT_FROM_PLL_ARM_MAIN_800M_CLK 0x01000000 +#define ARM_A7_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x03000000 +#define ARM_A7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define ARM_A7_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x05000000 +#define ARM_A7_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x02000000 +#define ARM_A7_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 +#define ARM_A7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* ARM_M4_CLK_ROOT */ +#define ARM_M4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ARM_M4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 +#define ARM_M4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define ARM_M4_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x03000000 +#define ARM_M4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x02000000 +#define ARM_M4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define ARM_M4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 +#define ARM_M4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* ARM_M0_CLK_ROOT */ +#define ARM_M0_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ARM_M0_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 +#define ARM_M0_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 +#define ARM_M0_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x03000000 +#define ARM_M0_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x02000000 +#define ARM_M0_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define ARM_M0_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 +#define ARM_M0_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* MAIN_AXI_CLK_ROOT */ +#define MAIN_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define MAIN_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000 +#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x04000000 +#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 +#define MAIN_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000 +#define MAIN_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define MAIN_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 + +/* DISP_AXI_CLK_ROOT */ +#define DISP_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define DISP_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000 +#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x04000000 +#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x05000000 +#define DISP_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000 +#define DISP_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 +#define DISP_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 + +/* ENET_AXI_CLK_ROOT */ +#define ENET_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ENET_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x04000000 +#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x01000000 +#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000 +#define ENET_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000 +#define ENET_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define ENET_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 + +/* NAND_USDHC_BUS_CLK_ROOT */ +#define NAND_USDHC_BUS_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x03000000 +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x01000000 +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x04000000 +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x05000000 +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000 + +/* AHB_CLK_ROOT */ +#define AHB_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define AHB_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define AHB_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x03000000 +#define AHB_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define AHB_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 +#define AHB_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 +#define AHB_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define AHB_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 + +/* DRAM_PHYM_CLK_ROOT */ +#define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x00000000 +#define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_PHYM_ALT_CLK_ROOT 0x01000000 + +/* DRAM_CLK_ROOT */ +#define DRAM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x00000000 +#define DRAM_CLK_ROOT_FROM_PLL_DRAM_ALT_CLK_ROOT 0x01000000 + +/* DRAM_PHYM_ALT_CLK_ROOT */ +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x01000000 +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x02000000 +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x05000000 +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000 + +/* DRAM_ALT_CLK_ROOT */ +#define DRAM_ALT_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define DRAM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x01000000 +#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x02000000 +#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x05000000 +#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x07000000 +#define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 +#define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x04000000 +#define DRAM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 + +/* USB_HSIC_CLK_ROOT */ +#define USB_HSIC_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000 +#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x03000000 +#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 +#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x05000000 +#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 +#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 +#define USB_HSIC_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x02000000 + +/* PCIE_CTRL_CLK_ROOT */ +#define PCIE_CTRL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x02000000 +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x06000000 +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x03000000 +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x07000000 +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000 +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x01000000 + +/* PCIE_PHY_CLK_ROOT */ +#define PCIE_PHY_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define PCIE_PHY_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x07000000 +#define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x02000000 +#define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_1 0x03000000 +#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_2 0x04000000 +#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 +#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 + +/* EPDC_PIXEL_CLK_ROOT */ +#define EPDC_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000 +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x04000000 +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x05000000 +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x06000000 +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 + +/* LCDIF_PIXEL_CLK_ROOT */ +#define LCDIF_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 +#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 +#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x01000000 +#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 +#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 +#define LCDIF_PIXEL_CLK_ROOT_FROM_EXT_CLK_3 0x03000000 + +/* MIPI_DSI_EXTSER_CLK_ROOT */ +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x05000000 +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK 0x04000000 +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x02000000 +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x01000000 +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000 +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 + +/* MIPI_CSI_WARP_CLK_ROOT */ +#define MIPI_CSI_WARP_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x05000000 +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK 0x04000000 +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x02000000 +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x01000000 +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000 +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 + +/* MIPI_DPHY_REF_CLK_ROOT */ +#define MIPI_DPHY_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 +#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x03000000 +#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 +#define MIPI_DPHY_REF_CLK_ROOT_FROM_REF_1M_CLK 0x04000000 +#define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 +#define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 + +/* SAI1_CLK_ROOT */ +#define SAI1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define SAI1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 +#define SAI1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 +#define SAI1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 +#define SAI1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 +#define SAI1_CLK_ROOT_FROM_EXT_CLK_2 0x07000000 + +/* SAI2_CLK_ROOT */ +#define SAI2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define SAI2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 +#define SAI2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 +#define SAI2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 +#define SAI2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 +#define SAI2_CLK_ROOT_FROM_EXT_CLK_2 0x07000000 + +/* SAI3_CLK_ROOT */ +#define SAI3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define SAI3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 +#define SAI3_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 +#define SAI3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 +#define SAI3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 +#define SAI3_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 + +/* SPDIF_CLK_ROOT */ +#define SPDIF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define SPDIF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 +#define SPDIF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 +#define SPDIF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 +#define SPDIF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 +#define SPDIF_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 + +/* ENET1_REF_CLK_ROOT */ +#define ENET1_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x04000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 +#define ENET1_REF_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 + +/* ENET1_TIME_CLK_ROOT */ +#define ENET1_TIME_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define ENET1_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 +#define ENET1_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_1 0x03000000 +#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_2 0x04000000 +#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 +#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 + +/* ENET2_REF_CLK_ROOT */ +#define ENET2_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ENET2_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x04000000 +#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 +#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 +#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 +#define ENET2_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define ENET2_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 +#define ENET2_REF_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 + +/* ENET2_TIME_CLK_ROOT */ +#define ENET2_TIME_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define ENET2_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 +#define ENET2_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_1 0x03000000 +#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_2 0x04000000 +#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 +#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 + +/* ENET_PHY_REF_CLK_ROOT */ +#define ENET_PHY_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x07000000 +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x03000000 +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000 +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 + +/* EIM_CLK_ROOT */ +#define EIM_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define EIM_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x04000000 +#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x05000000 +#define EIM_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 +#define EIM_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* NAND_CLK_ROOT */ +#define NAND_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define NAND_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define NAND_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000 +#define NAND_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x03000000 +#define NAND_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x04000000 +#define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000 +#define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 +#define NAND_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 + +/* QSPI_CLK_ROOT */ +#define QSPI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define QSPI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 +#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x04000000 +#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x01000000 +#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 +#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 +#define QSPI_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 + +/* USDHC1_CLK_ROOT */ +#define USDHC1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define USDHC1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000 +#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 +#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 +#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 +#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 +#define USDHC1_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 + +/* USDHC2_CLK_ROOT */ +#define USDHC2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define USDHC2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000 +#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 +#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 +#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 +#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 +#define USDHC2_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 + +/* USDHC3_CLK_ROOT */ +#define USDHC3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define USDHC3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000 +#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 +#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 +#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 +#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 +#define USDHC3_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 + +/* CAN1_CLK_ROOT */ +#define CAN1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define CAN1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 +#define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 +#define CAN1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x04000000 +#define CAN1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 +#define CAN1_CLK_ROOT_FROM_EXT_CLK_1 0x06000000 +#define CAN1_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 + +/* CAN2_CLK_ROOT */ +#define CAN2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define CAN2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 +#define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 +#define CAN2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x04000000 +#define CAN2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 +#define CAN2_CLK_ROOT_FROM_EXT_CLK_1 0x06000000 +#define CAN2_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 + +/* I2C1_CLK_ROOT */ +#define I2C1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define I2C1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 +#define I2C1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 +#define I2C1_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 +#define I2C1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define I2C1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 +#define I2C1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 + +/* I2C2_CLK_ROOT */ +#define I2C2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define I2C2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define I2C2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 +#define I2C2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 +#define I2C2_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 +#define I2C2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define I2C2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 +#define I2C2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 + +/* I2C3_CLK_ROOT */ +#define I2C3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define I2C3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define I2C3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 +#define I2C3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 +#define I2C3_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 +#define I2C3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define I2C3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 +#define I2C3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 + +/* I2C4_CLK_ROOT */ +#define I2C4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define I2C4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define I2C4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 +#define I2C4_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 +#define I2C4_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 +#define I2C4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define I2C4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 +#define I2C4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 + +/* UART1_CLK_ROOT */ +#define UART1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 +#define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define UART1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 +#define UART1_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 +#define UART1_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 + +/* UART2_CLK_ROOT */ +#define UART2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 +#define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define UART2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 +#define UART2_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 +#define UART2_CLK_ROOT_FROM_EXT_CLK_3 0x06000000 + +/* UART3_CLK_ROOT */ +#define UART3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 +#define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define UART3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 +#define UART3_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 +#define UART3_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 + +/* UART4_CLK_ROOT */ +#define UART4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 +#define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define UART4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 +#define UART4_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 +#define UART4_CLK_ROOT_FROM_EXT_CLK_3 0x06000000 + +/* UART5_CLK_ROOT */ +#define UART5_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 +#define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define UART5_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 +#define UART5_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 +#define UART5_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 + +/* UART6_CLK_ROOT */ +#define UART6_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 +#define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define UART6_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 +#define UART6_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 +#define UART6_CLK_ROOT_FROM_EXT_CLK_3 0x06000000 + +/* UART7_CLK_ROOT */ +#define UART7_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 +#define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define UART7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 +#define UART7_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 +#define UART7_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 + +/* ECSPI1_CLK_ROOT */ +#define ECSPI1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 +#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 +#define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 +#define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define ECSPI1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* ECSPI2_CLK_ROOT */ +#define ECSPI2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 +#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 +#define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 +#define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define ECSPI2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* ECSPI3_CLK_ROOT */ +#define ECSPI3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 +#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 +#define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 +#define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define ECSPI3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* ECSPI4_CLK_ROOT */ +#define ECSPI4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 +#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 +#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 +#define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 +#define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 +#define ECSPI4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* PWM1_CLK_ROOT */ +#define PWM1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define PWM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define PWM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define PWM1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define PWM1_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 +#define PWM1_CLK_ROOT_FROM_EXT_CLK_1 0x05000000 + +/* PWM2_CLK_ROOT */ +#define PWM2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define PWM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define PWM2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define PWM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define PWM2_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 +#define PWM2_CLK_ROOT_FROM_EXT_CLK_1 0x05000000 + +/* PWM3_CLK_ROOT */ +#define PWM3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define PWM3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define PWM3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define PWM3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define PWM3_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 +#define PWM3_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 + +/* PWM4_CLK_ROOT */ +#define PWM4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define PWM4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define PWM4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define PWM4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define PWM4_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 +#define PWM4_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 + +/* FLEXTIMER1_CLK_ROOT */ +#define FLEXTIMER1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define FLEXTIMER1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define FLEXTIMER1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define FLEXTIMER1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define FLEXTIMER1_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 +#define FLEXTIMER1_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 + +/* FLEXTIMER2_CLK_ROOT */ +#define FLEXTIMER2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define FLEXTIMER2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define FLEXTIMER2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 +#define FLEXTIMER2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 +#define FLEXTIMER2_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 +#define FLEXTIMER2_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 + +/* SIM1_CLK_ROOT */ +#define SIM1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define SIM1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define SIM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 +#define SIM1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 +#define SIM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define SIM1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000 + +/* SIM2_CLK_ROOT */ +#define SIM2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define SIM2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define SIM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 +#define SIM2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 +#define SIM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 +#define SIM2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000 + +/* GPT1_CLK_ROOT */ +#define GPT1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define GPT1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 +#define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define GPT1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 +#define GPT1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 +#define GPT1_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 +#define GPT1_CLK_ROOT_FROM_EXT_CLK_1 0x07000000 + +/* GPT2_CLK_ROOT */ +#define GPT2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define GPT2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 +#define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define GPT2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 +#define GPT2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 +#define GPT2_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 +#define GPT2_CLK_ROOT_FROM_EXT_CLK_2 0x07000000 + +/* GPT3_CLK_ROOT */ +#define GPT3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define GPT3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 +#define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define GPT3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 +#define GPT3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 +#define GPT3_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 +#define GPT3_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 + +/* GPT4_CLK_ROOT */ +#define GPT4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define GPT4_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 +#define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 +#define GPT4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 +#define GPT4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 +#define GPT4_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 +#define GPT4_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 + +/* TRACE_CLK_ROOT */ +#define TRACE_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define TRACE_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define TRACE_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define TRACE_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define TRACE_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 +#define TRACE_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 +#define TRACE_CLK_ROOT_FROM_EXT_CLK_1 0x06000000 +#define TRACE_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 + +/* WDOG_CLK_ROOT */ +#define WDOG_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define WDOG_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define WDOG_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD1_166M_CLK 0x07000000 +#define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define WDOG_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 +#define WDOG_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 +#define WDOG_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 + +/* CSI_MCLK_CLK_ROOT */ +#define CSI_MCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define CSI_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define CSI_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 +#define CSI_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define CSI_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 +#define CSI_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* AUDIO_MCLK_CLK_ROOT */ +#define AUDIO_MCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 + +/* WRCLK_CLK_ROOT */ +#define WRCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 +#define WRCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 +#define WRCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x04000000 +#define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 +#define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 +#define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x06000000 +#define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x01000000 +#define WRCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x03000000 + +/* IPP_DO_CLKO1 */ +#define IPP_DO_CLKO1_FROM_OSC_24M_CLK 0x00000000 +#define IPP_DO_CLKO1_FROM_PLL_DRAM_MAIN_533M_CLK 0x06000000 +#define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000 +#define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_240M_CLK 0x02000000 +#define IPP_DO_CLKO1_FROM_PLL_SYS_PFD0_196M_CLK 0x03000000 +#define IPP_DO_CLKO1_FROM_PLL_SYS_PFD3_CLK 0x04000000 +#define IPP_DO_CLKO1_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000 +#define IPP_DO_CLKO1_FROM_REF_1M_CLK 0x07000000 + +/* IPP_DO_CLKO2 */ +#define IPP_DO_CLKO2_FROM_OSC_24M_CLK 0x00000000 +#define IPP_DO_CLKO2_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 +#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 +#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD1_166M_CLK 0x03000000 +#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD4_CLK 0x04000000 +#define IPP_DO_CLKO2_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 +#define IPP_DO_CLKO2_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 +#define IPP_DO_CLKO2_FROM_OSC_32K_CLK 0x07000000 + +#endif diff --git a/arch/arm/include/asm/arch-mx7/gpio.h b/arch/arm/include/asm/arch-mx7/gpio.h new file mode 100644 index 0000000..b7890c2 --- /dev/null +++ b/arch/arm/include/asm/arch-mx7/gpio.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MX7_GPIO_H +#define __ASM_ARCH_MX7_GPIO_H + +#include <asm/imx-common/gpio.h> + +#endif /* __ASM_ARCH_MX7_GPIO_H */ diff --git a/arch/arm/include/asm/arch-mx7/hab.h b/arch/arm/include/asm/arch-mx7/hab.h new file mode 100644 index 0000000..fa29c78 --- /dev/null +++ b/arch/arm/include/asm/arch-mx7/hab.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + * +*/ + +#ifndef __SECURE_MX7_H__ +#define __SECURE_MX7_H__ + +#include <linux/types.h> + +/* -------- start of HAB API updates ------------*/ +/* The following are taken from HAB4 SIS */ + +/* Status definitions */ +enum hab_status { + HAB_STS_ANY = 0x00, + HAB_FAILURE = 0x33, + HAB_WARNING = 0x69, + HAB_SUCCESS = 0xf0 +}; + +/* Security Configuration definitions */ +enum hab_config { + HAB_CFG_RETURN = 0x33, /**< Field Return IC */ + HAB_CFG_OPEN = 0xf0, /**< Non-secure IC */ + HAB_CFG_CLOSED = 0xcc /**< Secure IC */ +}; + +/* State definitions */ +enum hab_state { + HAB_STATE_INITIAL = 0x33, /**< Initialising state (transitory) */ + HAB_STATE_CHECK = 0x55, /**< Check state (non-secure) */ + HAB_STATE_NONSECURE = 0x66, /**< Non-secure state */ + HAB_STATE_TRUSTED = 0x99, /**< Trusted state */ + HAB_STATE_SECURE = 0xaa, /**< Secure state */ + HAB_STATE_FAIL_SOFT = 0xcc, /**< Soft fail state */ + HAB_STATE_FAIL_HARD = 0xff, /**< Hard fail state (terminal) */ + HAB_STATE_NONE = 0xf0, /**< No security state machine */ + HAB_STATE_MAX +}; + +/*Function prototype description*/ +typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t, + uint8_t* , size_t*); +typedef enum hab_status hab_rvt_report_status_t(enum hab_config *, + enum hab_state *); +typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*); +typedef enum hab_status hab_rvt_entry_t(void); +typedef enum hab_status hab_rvt_exit_t(void); +typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t, + void **, size_t *, hab_loader_callback_f_t); +typedef void hapi_clock_init_t(void); + +#define HAB_RVT_UNIFIED_BASE 0x00000100 +#define HAB_RVT_ENTRY (*(uint32_t *) (HAB_RVT_UNIFIED_BASE + 0x04)) +#define HAB_RVT_EXIT (*(uint32_t *) (HAB_RVT_UNIFIED_BASE + 0x08)) +#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *) (HAB_RVT_UNIFIED_BASE + 0x10)) +#define HAB_RVT_REPORT_EVENT (*(uint32_t *) (HAB_RVT_UNIFIED_BASE + 0x20)) +#define HAB_RVT_REPORT_STATUS (*(uint32_t *) (HAB_RVT_UNIFIED_BASE + 0x24)) + +#define HAB_RVT_CLOCK_INIT ((hapi_clock_init_t *)0x0000024D) + +#define HAB_CID_ROM 0 /**< ROM Caller ID */ +#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/ +/* ----------- end of HAB API updates ------------*/ + +#endif diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h new file mode 100644 index 0000000..9f800ae --- /dev/null +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -0,0 +1,1303 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MX7_IMX_REGS_H__ +#define __ASM_ARCH_MX7_IMX_REGS_H__ + +#define ARCH_MXC + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define ROM_SW_INFO_ADDR 0x000001E8 +#define ROMCP_ARB_BASE_ADDR 0x00000000 +#define ROMCP_ARB_END_ADDR 0x00017FFF +#define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR +#define CAAM_ARB_BASE_ADDR 0x00100000 +#define CAAM_ARB_END_ADDR 0x00107FFF +#define GIC400_ARB_BASE_ADDR 0x31000000 +#define GIC400_ARB_END_ADDR 0x31007FFF +#define APBH_DMA_ARB_BASE_ADDR 0x33000000 +#define APBH_DMA_ARB_END_ADDR 0x33007FFF +#define M4_BOOTROM_BASE_ADDR 0x00180000 + +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) + +/* GPV - PL301 configuration ports */ +#define GPV0_BASE_ADDR 0x32000000 +#define GPV1_BASE_ADDR 0x32100000 +#define GPV2_BASE_ADDR 0x32200000 +#define GPV3_BASE_ADDR 0x32300000 +#define GPV4_BASE_ADDR 0x32400000 +#define GPV5_BASE_ADDR 0x32500000 +#define GPV6_BASE_ADDR 0x32600000 +#define GPV7_BASE_ADDR 0x32700000 + +#define OCRAM_ARB_BASE_ADDR 0x00900000 +#define OCRAM_ARB_END_ADDR 0x0091FFFF +#define OCRAM_EPDC_BASE_ADDR 0x00920000 +#define OCRAM_EPDC_END_ADDR 0x0093FFFF +#define OCRAM_PXP_BASE_ADDR 0x00940000 +#define OCRAM_PXP_END_ADDR 0x00947FFF +#define IRAM_BASE_ADDR OCRAM_ARB_BASE_ADDR +#define IRAM_SIZE 0x00020000 + +#define AIPS1_ARB_BASE_ADDR 0x30000000 +#define AIPS1_ARB_END_ADDR 0x303FFFFF +#define AIPS2_ARB_BASE_ADDR 0x30400000 +#define AIPS2_ARB_END_ADDR 0x307FFFFF +#define AIPS3_ARB_BASE_ADDR 0x30800000 +#define AIPS3_ARB_END_ADDR 0x30BFFFFF + +#define WEIM_ARB_BASE_ADDR 0x28000000 +#define WEIM_ARB_END_ADDR 0x2FFFFFFF + +#define QSPI0_ARB_BASE_ADDR 0x60000000 +#define QSPI0_ARB_END_ADDR 0x6FFFFFFF +#define PCIE_ARB_BASE_ADDR 0x40000000 +#define PCIE_ARB_END_ADDR 0x4FFFFFFF +#define PCIE_REG_BASE_ADDR 0x33800000 +#define PCIE_REG_END_ADDR 0x33803FFF + +#define MMDC0_ARB_BASE_ADDR 0x80000000 +#define MMDC0_ARB_END_ADDR 0xBFFFFFFF +#define MMDC1_ARB_BASE_ADDR 0xC0000000 +#define MMDC1_ARB_END_ADDR 0xFFFFFFFF + +/* Cortex-A9 MPCore private memory region */ +#define ARM_PERIPHBASE 0x31000000 +#define SCU_BASE_ADDR ARM_PERIPHBASE +#define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200) +#define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600) + + +/* Defines for Blocks connected via AIPS (SkyBlue) */ +#define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR +#define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR +#define AIPS_TZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR + +/* DAP base-address */ +#define ARM_IPS_BASE_ADDR AIPS1_ARB_BASE_ADDR + +/* AIPS_TZ#1- On Platform */ +#define AIPS1_ON_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x1F0000) +/* AIPS_TZ#1- Off Platform */ +#define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x200000) + +#define GPIO1_BASE_ADDR AIPS1_OFF_BASE_ADDR +#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x10000) +#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x20000) +#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x30000) +#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x40000) +#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x50000) +#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x60000) +#define IOMUXC_LPSR_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x70000) +#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x80000) +#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x90000) +#define WDOG3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xA0000) +#define WDOG4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xB0000) +#define IOMUXC_LPSR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xC0000) +#define GPT_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xD0000) +#define GPT1_BASE_ADDR GPT_IPS_BASE_ADDR +#define GPT2_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xE0000) +#define GPT3_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xF0000) +#define GPT4_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x100000) +#define ROMCP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x110000) +#define KPP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x120000) +#define IOMUXC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x130000) +#define IOMUXC_BASE_ADDR IOMUXC_IPS_BASE_ADDR +#define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x140000) +#define OCOTP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x150000) +#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x160000) +#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x170000) +#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x180000) +#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x190000) +#define GPC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1A0000) +#define SEMA41_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1B0000) +#define SEMA42_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1C0000) +#define RDC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1D0000) +#define CSU_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1E0000) + +/* AIPS_TZ#2- On Platform */ +#define AIPS2_ON_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x1F0000) +/* AIPS_TZ#2- Off Platform */ +#define AIPS2_OFF_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x200000) +#define ADC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x10000) +#define ADC2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x20000) +#define ECSPI4_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x30000) +#define FTM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x40000) +#define FTM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x50000) +#define PWM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x60000) +#define PWM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x70000) +#define PWM3_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x80000) +#define PWM4_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x90000) +#define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xA0000) +#define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xB0000) +#define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC0000) +#define PCIE_PHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xD0000) +#define EPDC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xF0000) +#define EPDC_BASE_ADDR EPDC_IPS_BASE_ADDR +#define EPXP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x100000) +#define CSI1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x110000) +#define ELCDIF1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x130000) +#define MIPI_CSI2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x150000) +#define MIPI_DSI_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x160000) +#define IP2APB_TZASC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x180000) +#define DDRPHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x190000) +#define DDRC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1A0000) +#define IP2APB_PERFMON1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1C0000) +#define IP2APB_PERFMON2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1D0000) +#define IP2APB_AXIMON_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1E0000) +#define QOSC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1F0000) + +/* AIPS_TZ#3 - Global enable (0) */ +#define ECSPI1_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x20000) +#define ECSPI2_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x30000) +#define ECSPI3_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x40000) +#define UART1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x60000) +#define UART3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x80000) +#define UART2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x90000) +#define SAI1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xA0000) +#define SAI2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xB0000) +#define SAI3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xC0000) +#define SPBA_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xF0000) +#define CAAM_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x100000) + +/* AIPS_TZ#3- On Platform */ +#define AIPS3_ON_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x1F0000) +/* AIPS_TZ#3- Off Platform */ +#define AIPS3_OFF_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x200000) +#define CAN1_IPS_BASE_ADDR AIPS3_OFF_BASE_ADDR +#define CAN2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x10000) +#define I2C1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x20000) +#define I2C2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x30000) +#define I2C3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x40000) +#define I2C4_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x50000) +#define UART4_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x60000) +#define UART5_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x70000) +#define UART6_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x80000) +#define UART7_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x90000) +#define MUCPU_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xA0000) +#define MUDSP_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xB0000) +#define HS_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xC0000) +#define USBOH2_PL301_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xD0000) +#define USBOTG1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x110000) +#define USBOTG2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x120000) +#define USBHSIC_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x130000) +#define USDHC1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x140000) +#define USDHC2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x150000) +#define USDHC3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x160000) +#define EMVSIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000) +#define EMVSIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000) +#define SIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000) +#define SIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000) +#define QSPI1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1B0000) +#define WEIM_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1C0000) +#define SDMA_PORT_IPS_HOST_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1D0000) +#define ENET_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1E0000) +#define ENET2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1F0000) + +#define SDMA_IPS_HOST_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR +#define SDMA_IPS_HOST_IPS_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR + +#define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR +#define DEBUG_MONITOR_BASE_ADDR IP2APB_AXIMON_IPS_BASE_ADDR + +#define USB_BASE_ADDR USBOTG1_IPS_BASE_ADDR + +#define FEC_QUIRK_ENET_MAC +#define SNVS_LPGPR 0x68 + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> + +extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); + +/* System Reset Controller (SRC) */ +struct src { + u32 scr; + u32 a7rcr0; + u32 a7rcr1; + u32 m4rcr; + u32 reserved1; + u32 ercr; + u32 reserved2; + u32 hsicphy_rcr; + u32 usbophy1_rcr; + u32 usbophy2_rcr; + u32 mipiphy_rcr; + u32 pciephy_rcr; + u32 reserved3[10]; + u32 sbmr1; + u32 srsr; + u32 reserved4[2]; + u32 sisr; + u32 simr; + u32 sbmr2; + u32 gpr1; + u32 gpr2; + u32 gpr3; + u32 gpr4; + u32 gpr5; + u32 gpr6; + u32 gpr7; + u32 gpr8; + u32 gpr9; + u32 gpr10; + u32 reserved5[985]; + u32 ddrc_rcr; +}; + +/* GPR0 Bit Fields */ +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6 +/* GPR1 Bit Fields */ +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0 +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK 0x6u +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT 1 +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK) +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_MASK 0x8u +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_SHIFT 3 +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK 0x30u +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT 4 +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK) +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_MASK 0x40u +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_SHIFT 6 +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK 0x180u +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT 7 +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK) +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_MASK 0x200u +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_SHIFT 9 +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK 0xC00u +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT 10 +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK) +#define IOMUXC_GPR_GPR1_GPR_IRQ_MASK 0x1000u +#define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT 12 +#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u +#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13 +#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK 0x4000u +#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_SHIFT 14 +#define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_MASK 0x8000u +#define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_SHIFT 15 +#define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_MASK 0x10000u +#define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_SHIFT 16 +#define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK 0x20000u +#define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_SHIFT 17 +#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK 0x40000u +#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_SHIFT 18 +#define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_MASK 0x400000u +#define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_SHIFT 22 +#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u +#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT 23 +#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK 0x30000000u +#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT 28 +#define IOMUXC_GPR_GPR1_GPR_DBG_ACK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT))&IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK) +#define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK 0x40000000u +#define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_SHIFT 30 +/* GPR2 Bit Fields */ +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_MASK 0x1u +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_SHIFT 0 +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_MASK 0x2u +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_SHIFT 1 +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_MASK 0x4u +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_SHIFT 2 +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_MASK 0x8u +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_SHIFT 3 +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_MASK 0x10u +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_SHIFT 4 +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_MASK 0x20u +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_SHIFT 5 +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_MASK 0x40u +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_SHIFT 6 +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_MASK 0x80u +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_SHIFT 7 +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_MASK 0x100u +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_SHIFT 8 +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_MASK 0x200u +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_SHIFT 9 +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_MASK 0x400u +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_SHIFT 10 +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_MASK 0x800u +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_SHIFT 11 +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_MASK 0x1000u +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_SHIFT 12 +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_MASK 0x2000u +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_SHIFT 13 +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_MASK 0x4000u +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_SHIFT 14 +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_MASK 0x8000u +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_SHIFT 15 +#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK 0xFF0000u +#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT 16 +#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT))&IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK) +#define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_MASK 0x1000000u +#define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_SHIFT 24 +#define IOMUXC_GPR_GPR2_GPR_MQS_EN_MASK 0x2000000u +#define IOMUXC_GPR_GPR2_GPR_MQS_EN_SHIFT 25 +#define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_MASK 0x4000000u +#define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_SHIFT 26 +#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_MASK 0x8000000u +#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_SHIFT 27 +#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_MASK 0x10000000u +#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_SHIFT 28 +#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_MASK 0x20000000u +#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_SHIFT 29 +#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_MASK 0x40000000u +#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_SHIFT 30 +#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_MASK 0x80000000u +#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_SHIFT 31 +/* GPR3 Bit Fields */ +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_MASK 0x1u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_SHIFT 0 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_MASK 0x2u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_SHIFT 1 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_MASK 0x4u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_SHIFT 2 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_MASK 0x8u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_SHIFT 3 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_MASK 0x10u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_SHIFT 4 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_MASK 0x20u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_SHIFT 5 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_MASK 0x40u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_SHIFT 6 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_MASK 0x80u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_SHIFT 7 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_MASK 0x100u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_SHIFT 8 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_MASK 0x200u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_SHIFT 9 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_MASK 0x400u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_SHIFT 10 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_MASK 0x800u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_SHIFT 11 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_MASK 0x1000u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_SHIFT 12 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_MASK 0x2000u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_SHIFT 13 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_MASK 0x4000u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_SHIFT 14 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_MASK 0x8000u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_SHIFT 15 +#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_MASK 0x10000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_SHIFT 16 +#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_MASK 0x20000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_SHIFT 17 +#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_MASK 0x40000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_SHIFT 18 +#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_MASK 0x80000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_SHIFT 19 +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_MASK 0x100000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_SHIFT 20 +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_MASK 0x200000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_SHIFT 21 +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_MASK 0x400000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_SHIFT 22 +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_MASK 0x800000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_SHIFT 23 +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_MASK 0x1000000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_SHIFT 24 +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_MASK 0x2000000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_SHIFT 25 +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_MASK 0x4000000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_SHIFT 26 +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_MASK 0x8000000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_SHIFT 27 +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_MASK 0x10000000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_SHIFT 28 +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_MASK 0x20000000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_SHIFT 29 +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_MASK 0x40000000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_SHIFT 30 +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_MASK 0x80000000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_SHIFT 31 +/* GPR4 Bit Fields */ +#define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_MASK 0x1u +#define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_SHIFT 0 +#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK 0x2u +#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT 1 +#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK 0x4u +#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT 2 +#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK 0x8u +#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT 3 +#define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_MASK 0x10u +#define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_SHIFT 4 +#define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_MASK 0x20u +#define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_SHIFT 5 +#define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_MASK 0x40u +#define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_SHIFT 6 +#define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_MASK 0x80u +#define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_SHIFT 7 +#define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_MASK 0x10000u +#define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_SHIFT 16 +#define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_MASK 0x20000u +#define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_SHIFT 17 +#define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_MASK 0x40000u +#define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_SHIFT 18 +#define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_MASK 0x80000u +#define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_SHIFT 19 +#define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_MASK 0x100000u +#define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_SHIFT 20 +#define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_MASK 0x200000u +#define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_SHIFT 21 +#define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_MASK 0x400000u +#define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_SHIFT 22 +#define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_MASK 0x800000u +#define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_SHIFT 23 +#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK 0x6000000u +#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT 25 +#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK) +#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK 0x18000000u +#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT 27 +#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK) +/* GPR5 Bit Fields */ +#define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_MASK 0x10u +#define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_SHIFT 4 +#define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_MASK 0x20u +#define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_SHIFT 5 +#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK 0x40u +#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT 6 +#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK 0x80u +#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT 7 +#define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_MASK 0x1000u +#define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_SHIFT 12 +#define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_MASK 0x80000u +#define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_SHIFT 19 +#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK 0x100000u +#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT 20 +#define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u +#define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_SHIFT 21 +#define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_MASK 0x400000u +#define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_SHIFT 22 +#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_MASK 0x1000000u +#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_SHIFT 24 +#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_MASK 0x2000000u +#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_SHIFT 25 +#define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_MASK 0x4000000u +#define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_SHIFT 26 +#define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_MASK 0x8000000u +#define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_SHIFT 27 +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_MASK 0x10000000u +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_SHIFT 28 +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_MASK 0x20000000u +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_SHIFT 29 +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_MASK 0x40000000u +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_SHIFT 30 +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_MASK 0x80000000u +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_SHIFT 31 +/* GPR6 Bit Fields */ +#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_MASK 0x1u +#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_SHIFT 0 +#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_MASK 0x2u +#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_SHIFT 1 +#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_MASK 0x4u +#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_SHIFT 2 +#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_MASK 0x8u +#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_SHIFT 3 +/* GPR7 Bit Fields */ +#define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_MASK 0x1u +#define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_SHIFT 0 +#define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_MASK 0x2u +#define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_SHIFT 1 +#define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_MASK 0x4u +#define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_SHIFT 2 +#define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_MASK 0x8u +#define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_SHIFT 3 +#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK 0x30u +#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT 4 +#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK) +#define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_MASK 0x40u +#define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_SHIFT 6 +#define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_MASK 0x80u +#define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_SHIFT 7 +#define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_MASK 0x100u +#define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_SHIFT 8 +#define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_MASK 0x200u +#define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_SHIFT 9 +#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK 0xC00u +#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT 10 +#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK) +#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_MASK 0x1000u +#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_SHIFT 12 +#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_MASK 0x2000u +#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_SHIFT 13 +/* GPR8 Bit Fields */ +#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK 0xF8u +#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT 3 +#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT))&IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK) +#define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK 0x100u +#define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_SHIFT 8 +/* GPR9 Bit Fields */ +#define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_MASK 0x1u +#define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_SHIFT 0 +#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK 0x3Eu +#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT 1 +#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT))&IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK) +/* GPR10 Bit Fields */ +#define IOMUXC_GPR_GPR10_GPR0_BF0_MASK 0x1u +#define IOMUXC_GPR_GPR10_GPR0_BF0_SHIFT 0 +#define IOMUXC_GPR_GPR10_GPR_DBG_EN_MASK 0x2u +#define IOMUXC_GPR_GPR10_GPR_DBG_EN_SHIFT 1 +#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK 0x4u +#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT 2 +#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_MASK 0x8u +#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_SHIFT 3 +#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK 0x3F0u +#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT 4 +#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK) +/* GPR11 Bit Fields */ +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK 0x1u +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT 0 +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK 0x3Eu +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT 1 +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK) +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_MASK 0x40u +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_SHIFT 6 +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK 0x380u +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT 7 +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK) +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK 0x400u +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT 10 +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK 0x3800u +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT 11 +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK) +/* GPR12 Bit Fields */ +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0 +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_SHIFT 1 +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_MASK 0x8u +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_SHIFT 3 +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_MASK 0x10u +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_SHIFT 4 +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_MASK 0x20u +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_SHIFT 5 +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT 12 +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK) +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT 17 +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK) +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT 21 +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK) +/* GPR13 Bit Fields */ +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK 0x1u +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT 0 +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK 0x2u +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT 1 +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_MASK 0x4u +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_SHIFT 2 +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_MASK 0x8u +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_SHIFT 3 +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK 0x10u +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT 4 +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK 0x20u +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT 5 +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_MASK 0x40u +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_SHIFT 6 +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_MASK 0x80u +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_SHIFT 7 +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_MASK 0x100u +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_SHIFT 8 +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_MASK 0x200u +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_SHIFT 9 +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK 0x400u +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT 10 +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK 0x800u +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT 11 +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_MASK 0x1000u +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_SHIFT 12 +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_MASK 0x2000u +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_SHIFT 13 +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_MASK 0x4000u +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_SHIFT 14 +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_MASK 0x8000u +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_SHIFT 15 +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT 16 +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK) +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK 0xF000000u +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT 24 +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK) +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_SHIFT 28 +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_SHIFT 29 +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_SHIFT 30 +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_SHIFT 31 +/* GPR14 Bit Fields */ +#define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_MASK 0x1u +#define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_SHIFT 0 +#define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_MASK 0x2u +#define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_SHIFT 1 +/* GPR15 Bit Fields */ +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_MASK 0x1u +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_SHIFT 0 +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_MASK 0x2u +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_SHIFT 1 +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT 2 +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK) +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT 16 +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK) +/* GPR16 Bit Fields */ +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK 0x3u +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT 0 +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK) +#define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_MASK 0x4u +#define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_SHIFT 2 +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_MASK 0x8u +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_SHIFT 3 +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_MASK 0x10u +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_SHIFT 4 +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_MASK 0x20u +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_SHIFT 5 +#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK 0x3C0u +#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT 6 +#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK) +#define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_MASK 0x400u +#define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_SHIFT 10 +#define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_MASK 0x800u +#define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_SHIFT 11 +#define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_MASK 0x1000u +#define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_SHIFT 12 +#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK 0xE000u +#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT 13 +#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK) +#define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_MASK 0x10000u +#define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_SHIFT 16 +#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_MASK 0x20000u +#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_SHIFT 17 +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK 0x180000u +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT 19 +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK) +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_MASK 0x200000u +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_SHIFT 21 +#define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_MASK 0x400000u +#define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_SHIFT 22 +#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_MASK 0x800000u +#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_SHIFT 23 +/* GPR17 Bit Fields */ +#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK 0xFFu +#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT 0 +#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK) +#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK 0xFF00u +#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT 8 +#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK) +/* GPR18 Bit Fields */ +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK 0x7u +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT 0 +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK) +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK 0x18u +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT 3 +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK) +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK 0x60u +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT 5 +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK) +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT 8 +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK) +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_SHIFT 14 +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT 16 +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK) +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT 24 +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK) +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_MASK 0x4000000u +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_SHIFT 26 +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_MASK 0x8000000u +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_SHIFT 27 +#define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_MASK 0x10000000u +#define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_SHIFT 28 +#define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_MASK 0x20000000u +#define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_SHIFT 29 +/* GPR19 Bit Fields */ +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_MASK 0x1u +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_SHIFT 0 +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT 8 +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT))&IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK) +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_MASK 0x10000u +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_SHIFT 16 +#define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_MASK 0x20000u +#define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_SHIFT 17 +/* GPR20 Bit Fields */ +#define IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK 0x3Fu +#define IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT 0 +#define IOMUXC_GPR_GPR20_GPR_LVDS_P(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK) +#define IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK 0x3F00u +#define IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT 8 +#define IOMUXC_GPR_GPR20_GPR_LVDS_M(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK) +#define IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK 0x30000u +#define IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT 16 +#define IOMUXC_GPR_GPR20_GPR_LVDS_S(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK) +#define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_MASK 0x1000000u +#define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_SHIFT 24 +#define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_MASK 0x2000000u +#define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_SHIFT 25 +#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u +#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT 27 +#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK) +/* GPR21 Bit Fields */ +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK 0x7u +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT 0 +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK) +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK 0x38u +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT 3 +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK) +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK 0x1C0u +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT 6 +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK) +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK 0xE00u +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT 9 +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK) +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK 0x7000u +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT 12 +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK) +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK 0x38000u +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT 15 +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK) +#define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_MASK 0x40000u +#define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_SHIFT 18 +#define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_MASK 0x80000u +#define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_SHIFT 19 +/* GPR22 Bit Fields */ +#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK 0xFF0000u +#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT 16 +#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT))&IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK) +#define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_MASK 0x1000000u +#define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_SHIFT 24 +#define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_MASK 0x2000000u +#define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_SHIFT 25 +#define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_MASK 0x4000000u +#define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_SHIFT 26 +#define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_MASK 0x8000000u +#define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_SHIFT 27 +#define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_MASK 0x10000000u +#define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_SHIFT 28 +#define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_MASK 0x20000000u +#define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_SHIFT 29 +#define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u +#define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_SHIFT 31 + +#define IMX7D_GPR5_CSI1_MUX_CTRL_MASK (0x1 << 4) +#define IMX7D_GPR5_CSI1_MUX_CTRL_PARALLEL_CSI (0x0 << 4) +#define IMX7D_GPR5_CSI1_MUX_CTRL_MIPI_CSI (0x1 << 4) + +struct iomuxc { + u32 gpr[23]; + /* mux and pad registers */ +}; + +struct iomuxc_gpr_base_regs { + u32 gpr[23]; /* 0x000 */ +}; + +/* ECSPI registers */ +struct cspi_regs { + u32 rxdata; + u32 txdata; + u32 ctrl; + u32 cfg; + u32 intr; + u32 dma; + u32 stat; + u32 period; +}; + +/* + * CSPI register definitions + */ +#define MXC_ECSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_MODE_MASK (0xf << 4) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) +#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) +#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 32 + +/* Bit position inside CTRL register to be associated with SS */ +#define MXC_CSPICTRL_CHAN 18 + +/* Bit position inside CON register to be associated with SS */ +#define MXC_CSPICON_PHA 0 /* SCLK phase control */ +#define MXC_CSPICON_POL 4 /* SCLK polarity */ +#define MXC_CSPICON_SSPOL 12 /* SS polarity */ +#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ + +#define MXC_SPI_BASE_ADDRESSES \ + ECSPI1_BASE_ADDR, \ + ECSPI2_BASE_ADDR, \ + ECSPI3_BASE_ADDR, \ + ECSPI4_BASE_ADDR + +struct ocotp_regs { + u32 ctrl; + u32 ctrl_set; + u32 ctrl_clr; + u32 ctrl_tog; + u32 timing; + u32 rsvd0[3]; + u32 data0; + u32 rsvd1[3]; + u32 data1; + u32 rsvd2[3]; + u32 data2; + u32 rsvd3[3]; + u32 data3; + u32 rsvd4[3]; + u32 read_ctrl; + u32 rsvd5[3]; + u32 read_fuse_data0; + u32 rsvd6[3]; + u32 read_fuse_data1; + u32 rsvd7[3]; + u32 read_fuse_data2; + u32 rsvd8[3]; + u32 read_fuse_data3; + u32 rsvd9[3]; + u32 sw_sticky; + u32 rsvd10[3]; + u32 scs; + u32 scs_set; + u32 scs_clr; + u32 scs_tog; + u32 crc_addr; + u32 rsvd11[3]; + u32 crc_value; + u32 rsvd12[3]; + u32 version; + u32 rsvd13[0xc3]; + + struct fuse_bank { /* offset 0x400 */ + u32 fuse_regs[0x10]; + } bank[16]; +}; + +struct fuse_bank0_regs { + u32 lock; + u32 rsvd0[3]; + u32 tester0; + u32 rsvd1[3]; + u32 tester1; + u32 rsvd2[3]; + u32 tester2; + u32 rsvd3[3]; +}; + +struct fuse_bank1_regs { + u32 tester3; + u32 rsvd0[3]; + u32 tester4; + u32 rsvd1[3]; + u32 tester5; + u32 rsvd2[3]; + u32 cfg0; + u32 rsvd3[3]; +}; + +struct fuse_bank2_regs { + u32 cfg1; + u32 rsvd0[3]; + u32 cfg2; + u32 rsvd1[3]; + u32 cfg3; + u32 rsvd2[3]; + u32 cfg4; + u32 rsvd3[3]; +}; + +struct fuse_bank3_regs { + u32 mem_trim0; + u32 rsvd0[3]; + u32 mem_trim1; + u32 rsvd1[3]; + u32 ana0; + u32 rsvd2[3]; + u32 ana1; + u32 rsvd3[3]; +}; + +struct fuse_bank8_regs { + u32 sjc_resp_low; + u32 rsvd0[3]; + u32 sjc_resp_high; + u32 rsvd1[3]; + u32 usb_id; + u32 rsvd2[3]; + u32 field_return; + u32 rsvd3[3]; +}; + +struct fuse_bank9_regs { + u32 mac_addr0; + u32 rsvd0[3]; + u32 mac_addr1; + u32 rsvd1[3]; + u32 mac_addr2; + u32 rsvd2[7]; +}; + +struct aipstz_regs { + u32 mprot0; + u32 mprot1; + u32 rsvd[0xe]; + u32 opacr0; + u32 opacr1; + u32 opacr2; + u32 opacr3; + u32 opacr4; +}; + +struct wdog_regs { + u16 wcr; /* Control */ + u16 wsr; /* Service */ + u16 wrsr; /* Reset Status */ + u16 wicr; /* Interrupt Control */ + u16 wmcr; /* Miscellaneous Control */ +}; + +struct dbg_monitor_regs { + u32 ctrl[4]; /* Control */ + u32 master_en[4]; /* Master enable */ + u32 irq[4]; /* IRQ */ + u32 trap_addr_low[4]; /* Trap address low */ + u32 trap_addr_high[4]; /* Trap address high */ + u32 trap_id[4]; /* Trap ID */ + u32 snvs_addr[4]; /* SNVS address */ + u32 snvs_data[4]; /* SNVS data */ + u32 snvs_info[4]; /* SNVS info */ + u32 version[4]; /* Version */ +}; + +struct rdc_regs { + u32 vir; /* Version information */ + u32 reserved1[8]; + u32 stat; /* Status */ + u32 intctrl; /* Interrupt and Control */ + u32 intstat; /* Interrupt Status */ + u32 reserved2[116]; + u32 mda[27]; /* Master Domain Assignment */ + u32 reserved3[101]; + u32 pdap[118]; /* Peripheral Domain Access Permissions */ + u32 reserved4[138]; + struct { + u32 mrsa; /* Memory Region Start Address */ + u32 mrea; /* Memory Region End Address */ + u32 mrc; /* Memory Region Control */ + u32 mrvs; /* Memory Region Violation Status */ + } mem_region[52]; +}; + +struct rdc_sema_regs { + u8 gate[64]; /* Gate */ + u16 rstgt; /* Reset Gate */ +}; + +/* eLCDIF controller registers */ +struct mxs_lcdif_regs { + u32 hw_lcdif_ctrl; /* 0x00 */ + u32 hw_lcdif_ctrl_set; + u32 hw_lcdif_ctrl_clr; + u32 hw_lcdif_ctrl_tog; + u32 hw_lcdif_ctrl1; /* 0x10 */ + u32 hw_lcdif_ctrl1_set; + u32 hw_lcdif_ctrl1_clr; + u32 hw_lcdif_ctrl1_tog; + u32 hw_lcdif_ctrl2; /* 0x20 */ + u32 hw_lcdif_ctrl2_set; + u32 hw_lcdif_ctrl2_clr; + u32 hw_lcdif_ctrl2_tog; + u32 hw_lcdif_transfer_count; /* 0x30 */ + u32 reserved1[3]; + u32 hw_lcdif_cur_buf; /* 0x40 */ + u32 reserved2[3]; + u32 hw_lcdif_next_buf; /* 0x50 */ + u32 reserved3[3]; + u32 hw_lcdif_timing; /* 0x60 */ + u32 reserved4[3]; + u32 hw_lcdif_vdctrl0; /* 0x70 */ + u32 hw_lcdif_vdctrl0_set; + u32 hw_lcdif_vdctrl0_clr; + u32 hw_lcdif_vdctrl0_tog; + u32 hw_lcdif_vdctrl1; /* 0x80 */ + u32 reserved5[3]; + u32 hw_lcdif_vdctrl2; /* 0x90 */ + u32 reserved6[3]; + u32 hw_lcdif_vdctrl3; /* 0xa0 */ + u32 reserved7[3]; + u32 hw_lcdif_vdctrl4; /* 0xb0 */ + u32 reserved8[3]; + u32 hw_lcdif_dvictrl0; /* 0xc0 */ + u32 reserved9[3]; + u32 hw_lcdif_dvictrl1; /* 0xd0 */ + u32 reserved10[3]; + u32 hw_lcdif_dvictrl2; /* 0xe0 */ + u32 reserved11[3]; + u32 hw_lcdif_dvictrl3; /* 0xf0 */ + u32 reserved12[3]; + u32 hw_lcdif_dvictrl4; /* 0x100 */ + u32 reserved13[3]; + u32 hw_lcdif_csc_coeffctrl0; /* 0x110 */ + u32 reserved14[3]; + u32 hw_lcdif_csc_coeffctrl1; /* 0x120 */ + u32 reserved15[3]; + u32 hw_lcdif_csc_coeffctrl2; /* 0x130 */ + u32 reserved16[3]; + u32 hw_lcdif_csc_coeffctrl3; /* 0x140 */ + u32 reserved17[3]; + u32 hw_lcdif_csc_coeffctrl4; /* 0x150 */ + u32 reserved18[3]; + u32 hw_lcdif_csc_offset; /* 0x160 */ + u32 reserved19[3]; + u32 hw_lcdif_csc_limit; /* 0x170 */ + u32 reserved20[3]; + u32 hw_lcdif_data; /* 0x180 */ + u32 reserved21[3]; + u32 hw_lcdif_bm_error_stat; /* 0x190 */ + u32 reserved22[3]; + u32 hw_lcdif_crc_stat; /* 0x1a0 */ + u32 reserved23[3]; + u32 hw_lcdif_lcdif_stat; /* 0x1b0 */ + u32 reserved24[3]; + u32 hw_lcdif_version; /* 0x1c0 */ + u32 reserved25[3]; + u32 hw_lcdif_debug0; /* 0x1d0 */ + u32 reserved26[3]; + u32 hw_lcdif_debug1; /* 0x1e0 */ + u32 reserved27[3]; + u32 hw_lcdif_debug2; /* 0x1f0 */ + u32 reserved28[3]; + u32 hw_lcdif_thres; /* 0x200 */ + u32 reserved29[3]; + u32 hw_lcdif_as_ctrl; /* 0x210 */ + u32 reserved30[3]; + u32 hw_lcdif_as_buf; /* 0x220 */ + u32 reserved31[3]; + u32 hw_lcdif_as_next_buf; /* 0x230 */ + u32 reserved32[3]; + u32 hw_lcdif_as_clrkeylow; /* 0x240 */ + u32 reserved33[3]; + u32 hw_lcdif_as_clrkeyhigh; /* 0x250 */ + u32 reserved34[3]; + u32 hw_lcdif_as_sync_delay; /* 0x260 */ + u32 reserved35[3]; + u32 hw_lcdif_as_debug3; /* 0x270 */ + u32 reserved36[3]; + u32 hw_lcdif_as_debug4; /* 0x280 */ + u32 reserved37[3]; + u32 hw_lcdif_as_debug5; /* 0x290 */ +}; + +#define MXS_LCDIF_BASE ELCDIF1_IPS_BASE_ADDR + +#define LCDIF_CTRL_SFTRST (1 << 31) +#define LCDIF_CTRL_CLKGATE (1 << 30) +#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29) +#define LCDIF_CTRL_READ_WRITEB (1 << 28) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27) +#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26) +#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21) +#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21 +#define LCDIF_CTRL_DVI_MODE (1 << 20) +#define LCDIF_CTRL_BYPASS_COUNT (1 << 19) +#define LCDIF_CTRL_VSYNC_MODE (1 << 18) +#define LCDIF_CTRL_DOTCLK_MODE (1 << 17) +#define LCDIF_CTRL_DATA_SELECT (1 << 16) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14 +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12 +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10 +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10) +#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8) +#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8 +#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8) +#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8) +#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8) +#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7) +#define LCDIF_CTRL_LCDIF_MASTER (1 << 5) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1) +#define LCDIF_CTRL_RUN (1 << 0) + +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26) +#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24) +#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22) +#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16 +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12) +#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11) +#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8) +#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2) +#define LCDIF_CTRL1_MODE86 (1 << 1) +#define LCDIF_CTRL1_RESET (1 << 0) + +#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21 +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21) +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21) +#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16 +#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12 +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12) +#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4 +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1) +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1 + +#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16) +#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16 +#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0) +#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0 + +#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff +#define LCDIF_CUR_BUF_ADDR_OFFSET 0 + +#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff +#define LCDIF_NEXT_BUF_ADDR_OFFSET 0 + +#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24) +#define LCDIF_TIMING_CMD_HOLD_OFFSET 24 +#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16) +#define LCDIF_TIMING_CMD_SETUP_OFFSET 16 +#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8) +#define LCDIF_TIMING_DATA_HOLD_OFFSET 8 +#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0) +#define LCDIF_TIMING_DATA_SETUP_OFFSET 0 + +#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29) +#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28) +#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27) +#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26) +#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25) +#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) +#define LCDIF_VDCTRL0_HALF_LINE (1 << 19) +#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0 + +#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff +#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0 + +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 +#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff +#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0 + +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) +#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16 +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0 + +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29 +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 + + +extern void check_cpu_temperature(void); + +extern void pcie_power_up(void); +extern void pcie_power_off(void); + +/* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB + * If boot from the other mode, USB0_PWD will keep reset value + */ +#define is_boot_from_usb(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \ + readl(USBOTG2_IPS_BASE_ADDR + 0x158)) +#define disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140) + +/* Boot device type */ +#define BOOT_TYPE_SD 0x1 +#define BOOT_TYPE_MMC 0x2 +#define BOOT_TYPE_NAND 0x3 +#define BOOT_TYPE_QSPI 0x4 +#define BOOT_TYPE_WEIM 0x5 +#define BOOT_TYPE_SPINOR 0x6 + +struct bootrom_sw_info { + u8 reserved_1; + u8 boot_dev_instance; + u8 boot_dev_type; + u8 reserved_2; + u32 arm_core_freq; + u32 axi_freq; + u32 ddr_freq; + u32 gpt1_freq; + u32 reserved_3[3]; +}; + +#endif /* __ASSEMBLER__*/ +#endif /* __ASM_ARCH_MX7_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx7/mx7-pins.h b/arch/arm/include/asm/arch-mx7/mx7-pins.h new file mode 100644 index 0000000..164c2be --- /dev/null +++ b/arch/arm/include/asm/arch-mx7/mx7-pins.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_ARCH_MX7_PINS_H__ +#define __ASM_ARCH_MX7_PINS_H__ + +#include <asm/imx-common/iomux-v3.h> + +#if defined(CONFIG_MX7D) +#include "mx7d_pins.h" +#elif defined(CONFIG_MX7S) +#include "mx7s_pins.h" +#else +#error "Please select cpu" +#endif /* CONFIG_MX7D */ + +#endif /*__ASM_ARCH_MX7_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx7/mx7d_pins.h b/arch/arm/include/asm/arch-mx7/mx7d_pins.h new file mode 100644 index 0000000..d8b4097 --- /dev/null +++ b/arch/arm/include/asm/arch-mx7/mx7d_pins.h @@ -0,0 +1,1308 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_IMX7D_PINS_H__ +#define __ASM_ARCH_IMX7D_PINS_H__ + +#include <asm/imx-common/iomux-v3.h> + +enum { + MX7D_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO00__PWM4_OUT = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO01__SAI1_MCLK = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO02__PWM2_OUT = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 2, 0x0564, 3, 0), + MX7D_PAD_GPIO1_IO02__SAI2_MCLK = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO02__CCM_CLKO1 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO02__USB_OTG1_ID = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 7, 0x0734, 3, 0), + + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO03__PWM3_OUT = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 2, 0x0570, 3, 0), + MX7D_PAD_GPIO1_IO03__SAI3_MCLK = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO03__CCM_CLKO2 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO03__USB_OTG2_ID = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 7, 0x0730, 3, 0), + + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO04__USB_OTG1_OC = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 1, 0x072C, 1, 0), + MX7D_PAD_GPIO1_IO04__FLEXTIMER_CH4 = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 2, 0x0594, 1, 0), + MX7D_PAD_GPIO1_IO04__UART5_CTS_B = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 3, 0x0710, 4, 0), + MX7D_PAD_GPIO1_IO04__I2C1_SCL = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05D4, 2, 0), + + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 2, 0x0598, 1, 0), + MX7D_PAD_GPIO1_IO05__UART5_RTS_B = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 3, 0x0710, 5, 0), + MX7D_PAD_GPIO1_IO05__I2C1_SDA = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05D8, 2, 0), + + MX7D_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO06__USB_OTG2_OC = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 1, 0x0728, 1, 0), + MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 2, 0x059C, 1, 0), + MX7D_PAD_GPIO1_IO06__UART5_RX_DATA = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 3, 0x0714, 4, 0), + MX7D_PAD_GPIO1_IO06__I2C2_SCL = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05DC, 2, 0), + MX7D_PAD_GPIO1_IO06__CCM_WAIT = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO06__KPP_ROW4 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 6, 0x0624, 1, 0), + + MX7D_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 2, 0x05A0, 1, 0), + MX7D_PAD_GPIO1_IO07__UART5_TX_DATA = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 3, 0x0714, 5, 0), + MX7D_PAD_GPIO1_IO07__I2C2_SDA = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05E0, 2, 0), + MX7D_PAD_GPIO1_IO07__CCM_STOP = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO07__KPP_COL4 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 6, 0x0604, 1, 0), +}; + +enum { + MX7D_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x026C, 0x0014, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO08__SD1_VSELECT = IOMUX_PAD(0x026C, 0x0014, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x026C, 0x0014, 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO08__UART3_DCE_RX = IOMUX_PAD(0x026C, 0x0014, 3, 0x0704, 0, 0), + MX7D_PAD_GPIO1_IO08__UART3_DTE_TX = IOMUX_PAD(0x026C, 0x0014, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO08__I2C3_SCL = IOMUX_PAD(0x026C, 0x0014, IOMUX_CONFIG_SION | 4, 0x05E4, 0, 0), + MX7D_PAD_GPIO1_IO08__KPP_COL5 = IOMUX_PAD(0x026C, 0x0014, 6, 0x0608, 0, 0), + MX7D_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x026C, 0x0014, 7, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x0270, 0x0018, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO09__SD1_LCTL = IOMUX_PAD(0x0270, 0x0018, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x0270, 0x0018, 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO09__UART3_DCE_TX = IOMUX_PAD(0x0270, 0x0018, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO09__UART3_DTE_RX = IOMUX_PAD(0x0270, 0x0018, 3, 0x0704, 1, 0), + MX7D_PAD_GPIO1_IO09__I2C3_SDA = IOMUX_PAD(0x0270, 0x0018, IOMUX_CONFIG_SION | 4, 0x05E8, 0, 0), + MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY = IOMUX_PAD(0x0270, 0x0018, 5, 0x04F4, 0, 0), + MX7D_PAD_GPIO1_IO09__KPP_ROW5 = IOMUX_PAD(0x0270, 0x0018, 6, 0x0628, 0, 0), + MX7D_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x0270, 0x0018, 7, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x0274, 0x001C, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO10__SD2_LCTL = IOMUX_PAD(0x0274, 0x001C, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO10__ENET1_MDIO = IOMUX_PAD(0x0274, 0x001C, 2, 0x0568, 0, 0), + MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS = IOMUX_PAD(0x0274, 0x001C, 3, 0x0700, 0, 0), + MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS = IOMUX_PAD(0x0274, 0x001C, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO10__I2C4_SCL = IOMUX_PAD(0x0274, 0x001C, IOMUX_CONFIG_SION | 4, 0x05EC, 0, 0), + MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA = IOMUX_PAD(0x0274, 0x001C, 5, 0x05A4, 0, 0), + MX7D_PAD_GPIO1_IO10__KPP_COL6 = IOMUX_PAD(0x0274, 0x001C, 6, 0x060C, 0, 0), + MX7D_PAD_GPIO1_IO10__PWM3_OUT = IOMUX_PAD(0x0274, 0x001C, 7, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x0278, 0x0020, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO11__SD3_LCTL = IOMUX_PAD(0x0278, 0x0020, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO11__ENET1_MDC = IOMUX_PAD(0x0278, 0x0020, 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS = IOMUX_PAD(0x0278, 0x0020, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS = IOMUX_PAD(0x0278, 0x0020, 3, 0x0700, 1, 0), + MX7D_PAD_GPIO1_IO11__I2C4_SDA = IOMUX_PAD(0x0278, 0x0020, IOMUX_CONFIG_SION | 4, 0x05F0, 0, 0), + MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB = IOMUX_PAD(0x0278, 0x0020, 5, 0x05A8, 0, 0), + MX7D_PAD_GPIO1_IO11__KPP_ROW6 = IOMUX_PAD(0x0278, 0x0020, 6, 0x062C, 0, 0), + MX7D_PAD_GPIO1_IO11__PWM4_OUT = IOMUX_PAD(0x0278, 0x0020, 7, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x027C, 0x0024, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO12__SD2_VSELECT = IOMUX_PAD(0x027C, 0x0024, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x027C, 0x0024, 2, 0x0564, 0, 0), + MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX = IOMUX_PAD(0x027C, 0x0024, 3, 0x04DC, 0, 0), + MX7D_PAD_GPIO1_IO12__CM4_NMI = IOMUX_PAD(0x027C, 0x0024, 4, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 = IOMUX_PAD(0x027C, 0x0024, 5, 0x04E4, 0, 0), + MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 = IOMUX_PAD(0x027C, 0x0024, 6, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO12__USB_OTG1_ID = IOMUX_PAD(0x027C, 0x0024, 7, 0x0734, 0, 0), + + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x0280, 0x0028, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO13__SD3_VSELECT = IOMUX_PAD(0x0280, 0x0028, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x0280, 0x0028, 2, 0x0570, 0, 0), + MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX = IOMUX_PAD(0x0280, 0x0028, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY = IOMUX_PAD(0x0280, 0x0028, 4, 0x04F4, 1, 0), + MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 = IOMUX_PAD(0x0280, 0x0028, 5, 0x04E8, 0, 0), + MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL = IOMUX_PAD(0x0280, 0x0028, 6, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO13__USB_OTG2_ID = IOMUX_PAD(0x0280, 0x0028, 7, 0x0730, 0, 0), + + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x0284, 0x002C, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO14__SD3_CD_B = IOMUX_PAD(0x0284, 0x002C, 1, 0x0738, 0, 0), + MX7D_PAD_GPIO1_IO14__ENET2_MDIO = IOMUX_PAD(0x0284, 0x002C, 2, 0x0574, 0, 0), + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX = IOMUX_PAD(0x0284, 0x002C, 3, 0x04E0, 0, 0), + MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B = IOMUX_PAD(0x0284, 0x002C, 4, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 = IOMUX_PAD(0x0284, 0x002C, 5, 0x04EC, 0, 0), + MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 = IOMUX_PAD(0x0284, 0x002C, 6, 0x06D8, 0, 0), + + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x0288, 0x0030, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO15__SD3_WP = IOMUX_PAD(0x0288, 0x0030, 1, 0x073C, 0, 0), + MX7D_PAD_GPIO1_IO15__ENET2_MDC = IOMUX_PAD(0x0288, 0x0030, 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX = IOMUX_PAD(0x0288, 0x0030, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B = IOMUX_PAD(0x0288, 0x0030, 4, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 = IOMUX_PAD(0x0288, 0x0030, 5, 0x04F0, 0, 0), + MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0288, 0x0030, 6, 0x06DC, 0, 0), + + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD = IOMUX_PAD(0x02A4, 0x0034, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__KPP_ROW3 = IOMUX_PAD(0x02A4, 0x0034, 3, 0x0620, 0, 0), + MX7D_PAD_EPDC_DATA00__EIM_AD0 = IOMUX_PAD(0x02A4, 0x0034, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 = IOMUX_PAD(0x02A4, 0x0034, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__LCD_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 6, 0x0638, 0, 0), + MX7D_PAD_EPDC_DATA00__LCD_CLK = IOMUX_PAD(0x02A4, 0x0034, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK = IOMUX_PAD(0x02A8, 0x0038, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__KPP_COL3 = IOMUX_PAD(0x02A8, 0x0038, 3, 0x0600, 0, 0), + MX7D_PAD_EPDC_DATA01__EIM_AD1 = IOMUX_PAD(0x02A8, 0x0038, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 = IOMUX_PAD(0x02A8, 0x0038, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__LCD_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 6, 0x063C, 0, 0), + MX7D_PAD_EPDC_DATA01__LCD_ENABLE = IOMUX_PAD(0x02A8, 0x0038, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B = IOMUX_PAD(0x02AC, 0x003C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__KPP_ROW2 = IOMUX_PAD(0x02AC, 0x003C, 3, 0x061C, 0, 0), + MX7D_PAD_EPDC_DATA02__EIM_AD2 = IOMUX_PAD(0x02AC, 0x003C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 = IOMUX_PAD(0x02AC, 0x003C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__LCD_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 6, 0x0640, 0, 0), + MX7D_PAD_EPDC_DATA02__LCD_VSYNC = IOMUX_PAD(0x02AC, 0x003C, 7, 0x0698, 0, 0), + + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN = IOMUX_PAD(0x02B0, 0x0040, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__KPP_COL2 = IOMUX_PAD(0x02B0, 0x0040, 3, 0x05FC, 0, 0), + MX7D_PAD_EPDC_DATA03__EIM_AD3 = IOMUX_PAD(0x02B0, 0x0040, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 = IOMUX_PAD(0x02B0, 0x0040, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__LCD_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 6, 0x0644, 0, 0), + MX7D_PAD_EPDC_DATA03__LCD_HSYNC = IOMUX_PAD(0x02B0, 0x0040, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 = IOMUX_PAD(0x02B4, 0x0044, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD = IOMUX_PAD(0x02B4, 0x0044, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS = IOMUX_PAD(0x02B4, 0x0044, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__KPP_ROW1 = IOMUX_PAD(0x02B4, 0x0044, 3, 0x0618, 0, 0), + MX7D_PAD_EPDC_DATA04__EIM_AD4 = IOMUX_PAD(0x02B4, 0x0044, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 = IOMUX_PAD(0x02B4, 0x0044, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__LCD_DATA4 = IOMUX_PAD(0x02B4, 0x0044, 6, 0x0648, 0, 0), + MX7D_PAD_EPDC_DATA04__JTAG_FAIL = IOMUX_PAD(0x02B4, 0x0044, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 = IOMUX_PAD(0x02B8, 0x0048, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD = IOMUX_PAD(0x02B8, 0x0048, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK = IOMUX_PAD(0x02B8, 0x0048, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__KPP_COL1 = IOMUX_PAD(0x02B8, 0x0048, 3, 0x05F8, 0, 0), + MX7D_PAD_EPDC_DATA05__EIM_AD5 = IOMUX_PAD(0x02B8, 0x0048, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 = IOMUX_PAD(0x02B8, 0x0048, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__LCD_DATA5 = IOMUX_PAD(0x02B8, 0x0048, 6, 0x064C, 0, 0), + MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE = IOMUX_PAD(0x02B8, 0x0048, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 = IOMUX_PAD(0x02BC, 0x004C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK = IOMUX_PAD(0x02BC, 0x004C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B = IOMUX_PAD(0x02BC, 0x004C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__KPP_ROW0 = IOMUX_PAD(0x02BC, 0x004C, 3, 0x0614, 0, 0), + MX7D_PAD_EPDC_DATA06__EIM_AD6 = IOMUX_PAD(0x02BC, 0x004C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__GPIO2_IO6 = IOMUX_PAD(0x02BC, 0x004C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__LCD_DATA6 = IOMUX_PAD(0x02BC, 0x004C, 6, 0x0650, 0, 0), + MX7D_PAD_EPDC_DATA06__JTAG_DE_B = IOMUX_PAD(0x02BC, 0x004C, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 = IOMUX_PAD(0x02C0, 0x0050, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B = IOMUX_PAD(0x02C0, 0x0050, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B = IOMUX_PAD(0x02C0, 0x0050, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__KPP_COL0 = IOMUX_PAD(0x02C0, 0x0050, 3, 0x05F4, 0, 0), + MX7D_PAD_EPDC_DATA07__EIM_AD7 = IOMUX_PAD(0x02C0, 0x0050, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 = IOMUX_PAD(0x02C0, 0x0050, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__LCD_DATA7 = IOMUX_PAD(0x02C0, 0x0050, 6, 0x0654, 0, 0), + MX7D_PAD_EPDC_DATA07__JTAG_DONE = IOMUX_PAD(0x02C0, 0x0050, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA08__EPDC_DATA8 = IOMUX_PAD(0x02C4, 0x0054, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD = IOMUX_PAD(0x02C4, 0x0054, 1, 0x06E4, 0, 0), + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 = IOMUX_PAD(0x02C4, 0x0054, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__UART6_DCE_RX = IOMUX_PAD(0x02C4, 0x0054, 3, 0x071C, 0, 0), + MX7D_PAD_EPDC_DATA08__UART6_DTE_TX = IOMUX_PAD(0x02C4, 0x0054, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__EIM_OE = IOMUX_PAD(0x02C4, 0x0054, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 = IOMUX_PAD(0x02C4, 0x0054, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__LCD_DATA8 = IOMUX_PAD(0x02C4, 0x0054, 6, 0x0658, 0, 0), + MX7D_PAD_EPDC_DATA08__LCD_BUSY = IOMUX_PAD(0x02C4, 0x0054, 7, 0x0634, 0, 0), + MX7D_PAD_EPDC_DATA08__EPDC_SDCLK = IOMUX_PAD(0x02C4, 0x0054, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA09__EPDC_DATA9 = IOMUX_PAD(0x02C8, 0x0058, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK = IOMUX_PAD(0x02C8, 0x0058, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 = IOMUX_PAD(0x02C8, 0x0058, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__UART6_DCE_TX = IOMUX_PAD(0x02C8, 0x0058, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__UART6_DTE_RX = IOMUX_PAD(0x02C8, 0x0058, 3, 0x071C, 1, 0), + MX7D_PAD_EPDC_DATA09__EIM_RW = IOMUX_PAD(0x02C8, 0x0058, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__GPIO2_IO9 = IOMUX_PAD(0x02C8, 0x0058, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__LCD_DATA9 = IOMUX_PAD(0x02C8, 0x0058, 6, 0x065C, 0, 0), + MX7D_PAD_EPDC_DATA09__LCD_DATA0 = IOMUX_PAD(0x02C8, 0x0058, 7, 0x0638, 1, 0), + MX7D_PAD_EPDC_DATA09__EPDC_SDLE = IOMUX_PAD(0x02C8, 0x0058, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA10__EPDC_DATA10 = IOMUX_PAD(0x02CC, 0x005C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B = IOMUX_PAD(0x02CC, 0x005C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 = IOMUX_PAD(0x02CC, 0x005C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS = IOMUX_PAD(0x02CC, 0x005C, 3, 0x0718, 0, 0), + MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS = IOMUX_PAD(0x02CC, 0x005C, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__EIM_CS0_B = IOMUX_PAD(0x02CC, 0x005C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__GPIO2_IO10 = IOMUX_PAD(0x02CC, 0x005C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__LCD_DATA10 = IOMUX_PAD(0x02CC, 0x005C, 6, 0x0660, 0, 0), + MX7D_PAD_EPDC_DATA10__LCD_DATA9 = IOMUX_PAD(0x02CC, 0x005C, 7, 0x065C, 1, 0), + MX7D_PAD_EPDC_DATA10__EPDC_SDOE = IOMUX_PAD(0x02CC, 0x005C, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA11__EPDC_DATA11 = IOMUX_PAD(0x02D0, 0x0060, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN = IOMUX_PAD(0x02D0, 0x0060, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 = IOMUX_PAD(0x02D0, 0x0060, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS = IOMUX_PAD(0x02D0, 0x0060, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS = IOMUX_PAD(0x02D0, 0x0060, 3, 0x0718, 1, 0), + MX7D_PAD_EPDC_DATA11__EIM_BCLK = IOMUX_PAD(0x02D0, 0x0060, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__GPIO2_IO11 = IOMUX_PAD(0x02D0, 0x0060, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__LCD_DATA11 = IOMUX_PAD(0x02D0, 0x0060, 6, 0x0664, 0, 0), + MX7D_PAD_EPDC_DATA11__LCD_DATA1 = IOMUX_PAD(0x02D0, 0x0060, 7, 0x063C, 1, 0), + MX7D_PAD_EPDC_DATA11__EPDC_SDCE0 = IOMUX_PAD(0x02D0, 0x0060, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA12__EPDC_DATA12 = IOMUX_PAD(0x02D4, 0x0064, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD = IOMUX_PAD(0x02D4, 0x0064, 1, 0x06E0, 0, 0), + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS = IOMUX_PAD(0x02D4, 0x0064, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__UART7_DCE_RX = IOMUX_PAD(0x02D4, 0x0064, 3, 0x0724, 0, 0), + MX7D_PAD_EPDC_DATA12__UART7_DTE_TX = IOMUX_PAD(0x02D4, 0x0064, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__EIM_LBA_B = IOMUX_PAD(0x02D4, 0x0064, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__GPIO2_IO12 = IOMUX_PAD(0x02D4, 0x0064, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__LCD_DATA12 = IOMUX_PAD(0x02D4, 0x0064, 6, 0x0668, 0, 0), + MX7D_PAD_EPDC_DATA12__LCD_DATA21 = IOMUX_PAD(0x02D4, 0x0064, 7, 0x068C, 0, 0), + MX7D_PAD_EPDC_DATA12__EPDC_GDCLK = IOMUX_PAD(0x02D4, 0x0064, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA13__EPDC_DATA13 = IOMUX_PAD(0x02D8, 0x0068, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD = IOMUX_PAD(0x02D8, 0x0068, 1, 0x06EC, 0, 0), + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK = IOMUX_PAD(0x02D8, 0x0068, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__UART7_DCE_TX = IOMUX_PAD(0x02D8, 0x0068, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__UART7_DTE_RX = IOMUX_PAD(0x02D8, 0x0068, 3, 0x0724, 1, 0), + MX7D_PAD_EPDC_DATA13__EIM_WAIT = IOMUX_PAD(0x02D8, 0x0068, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 = IOMUX_PAD(0x02D8, 0x0068, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__LCD_DATA13 = IOMUX_PAD(0x02D8, 0x0068, 6, 0x066C, 0, 0), + MX7D_PAD_EPDC_DATA13__LCD_CS = IOMUX_PAD(0x02D8, 0x0068, 7, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__EPDC_GDOE = IOMUX_PAD(0x02D8, 0x0068, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA14__EPDC_DATA14 = IOMUX_PAD(0x02DC, 0x006C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK = IOMUX_PAD(0x02DC, 0x006C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B = IOMUX_PAD(0x02DC, 0x006C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS = IOMUX_PAD(0x02DC, 0x006C, 3, 0x0720, 0, 0), + MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS = IOMUX_PAD(0x02DC, 0x006C, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__EIM_EB_B0 = IOMUX_PAD(0x02DC, 0x006C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__GPIO2_IO14 = IOMUX_PAD(0x02DC, 0x006C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__LCD_DATA14 = IOMUX_PAD(0x02DC, 0x006C, 6, 0x0670, 0, 0), + MX7D_PAD_EPDC_DATA14__LCD_DATA22 = IOMUX_PAD(0x02DC, 0x006C, 7, 0x0690, 0, 0), + MX7D_PAD_EPDC_DATA14__EPDC_GDSP = IOMUX_PAD(0x02DC, 0x006C, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA15__EPDC_DATA15 = IOMUX_PAD(0x02E0, 0x0070, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B = IOMUX_PAD(0x02E0, 0x0070, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B = IOMUX_PAD(0x02E0, 0x0070, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS = IOMUX_PAD(0x02E0, 0x0070, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS = IOMUX_PAD(0x02E0, 0x0070, 3, 0x0720, 1, 0), + MX7D_PAD_EPDC_DATA15__EIM_CS1_B = IOMUX_PAD(0x02E0, 0x0070, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__GPIO2_IO15 = IOMUX_PAD(0x02E0, 0x0070, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__LCD_DATA15 = IOMUX_PAD(0x02E0, 0x0070, 6, 0x0674, 0, 0), + MX7D_PAD_EPDC_DATA15__LCD_WR_RWN = IOMUX_PAD(0x02E0, 0x0070, 7, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM = IOMUX_PAD(0x02E0, 0x0070, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK = IOMUX_PAD(0x02E4, 0x0074, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN = IOMUX_PAD(0x02E4, 0x0074, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 = IOMUX_PAD(0x02E4, 0x0074, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__KPP_ROW4 = IOMUX_PAD(0x02E4, 0x0074, 3, 0x0624, 0, 0), + MX7D_PAD_EPDC_SDCLK__EIM_AD10 = IOMUX_PAD(0x02E4, 0x0074, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 = IOMUX_PAD(0x02E4, 0x0074, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__LCD_CLK = IOMUX_PAD(0x02E4, 0x0074, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__LCD_DATA20 = IOMUX_PAD(0x02E4, 0x0074, 7, 0x0688, 0, 0), + + MX7D_PAD_EPDC_SDLE__EPDC_SDLE = IOMUX_PAD(0x02E8, 0x0078, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD = IOMUX_PAD(0x02E8, 0x0078, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 = IOMUX_PAD(0x02E8, 0x0078, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__KPP_COL4 = IOMUX_PAD(0x02E8, 0x0078, 3, 0x0604, 0, 0), + MX7D_PAD_EPDC_SDLE__EIM_AD11 = IOMUX_PAD(0x02E8, 0x0078, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__GPIO2_IO17 = IOMUX_PAD(0x02E8, 0x0078, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__LCD_DATA16 = IOMUX_PAD(0x02E8, 0x0078, 6, 0x0678, 0, 0), + MX7D_PAD_EPDC_SDLE__LCD_DATA8 = IOMUX_PAD(0x02E8, 0x0078, 7, 0x0658, 1, 0), + + MX7D_PAD_EPDC_SDOE__EPDC_SDOE = IOMUX_PAD(0x02EC, 0x007C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0 = IOMUX_PAD(0x02EC, 0x007C, 1, 0x0584, 0, 0), + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 = IOMUX_PAD(0x02EC, 0x007C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDOE__KPP_COL5 = IOMUX_PAD(0x02EC, 0x007C, 3, 0x0608, 1, 0), + MX7D_PAD_EPDC_SDOE__EIM_AD12 = IOMUX_PAD(0x02EC, 0x007C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDOE__GPIO2_IO18 = IOMUX_PAD(0x02EC, 0x007C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDOE__LCD_DATA17 = IOMUX_PAD(0x02EC, 0x007C, 6, 0x067C, 0, 0), + MX7D_PAD_EPDC_SDOE__LCD_DATA23 = IOMUX_PAD(0x02EC, 0x007C, 7, 0x0694, 0, 0), + + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR = IOMUX_PAD(0x02F0, 0x0080, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1 = IOMUX_PAD(0x02F0, 0x0080, 1, 0x0588, 0, 0), + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 = IOMUX_PAD(0x02F0, 0x0080, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDSHR__KPP_ROW5 = IOMUX_PAD(0x02F0, 0x0080, 3, 0x0628, 1, 0), + MX7D_PAD_EPDC_SDSHR__EIM_AD13 = IOMUX_PAD(0x02F0, 0x0080, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 = IOMUX_PAD(0x02F0, 0x0080, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDSHR__LCD_DATA18 = IOMUX_PAD(0x02F0, 0x0080, 6, 0x0680, 0, 0), + MX7D_PAD_EPDC_SDSHR__LCD_DATA10 = IOMUX_PAD(0x02F0, 0x0080, 7, 0x0660, 1, 0), + + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 = IOMUX_PAD(0x02F4, 0x0084, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2 = IOMUX_PAD(0x02F4, 0x0084, 1, 0x058C, 0, 0), + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL = IOMUX_PAD(0x02F4, 0x0084, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE0__EIM_AD14 = IOMUX_PAD(0x02F4, 0x0084, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 = IOMUX_PAD(0x02F4, 0x0084, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE0__LCD_DATA19 = IOMUX_PAD(0x02F4, 0x0084, 6, 0x0684, 0, 0), + MX7D_PAD_EPDC_SDCE0__LCD_DATA5 = IOMUX_PAD(0x02F4, 0x0084, 7, 0x064C, 1, 0), + + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 = IOMUX_PAD(0x02F8, 0x0088, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3 = IOMUX_PAD(0x02F8, 0x0088, 1, 0x0590, 0, 0), + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC = IOMUX_PAD(0x02F8, 0x0088, 2, 0x0578, 0, 0), + MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER = IOMUX_PAD(0x02F8, 0x0088, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE1__EIM_AD15 = IOMUX_PAD(0x02F8, 0x0088, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 = IOMUX_PAD(0x02F8, 0x0088, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE1__LCD_DATA20 = IOMUX_PAD(0x02F8, 0x0088, 6, 0x0688, 1, 0), + MX7D_PAD_EPDC_SDCE1__LCD_DATA4 = IOMUX_PAD(0x02F8, 0x0088, 7, 0x0648, 1, 0), + + MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 = IOMUX_PAD(0x02FC, 0x008C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN = IOMUX_PAD(0x02FC, 0x008C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 = IOMUX_PAD(0x02FC, 0x008C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__KPP_COL6 = IOMUX_PAD(0x02FC, 0x008C, 3, 0x060C, 1, 0), + MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 = IOMUX_PAD(0x02FC, 0x008C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 = IOMUX_PAD(0x02FC, 0x008C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__LCD_DATA21 = IOMUX_PAD(0x02FC, 0x008C, 6, 0x068C, 1, 0), + MX7D_PAD_EPDC_SDCE2__LCD_DATA3 = IOMUX_PAD(0x02FC, 0x008C, 7, 0x0644, 1, 0), + + MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 = IOMUX_PAD(0x0300, 0x0090, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD = IOMUX_PAD(0x0300, 0x0090, 1, 0x06E8, 0, 0), + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 = IOMUX_PAD(0x0300, 0x0090, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE3__KPP_ROW6 = IOMUX_PAD(0x0300, 0x0090, 3, 0x062C, 1, 0), + MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 = IOMUX_PAD(0x0300, 0x0090, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 = IOMUX_PAD(0x0300, 0x0090, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE3__LCD_DATA22 = IOMUX_PAD(0x0300, 0x0090, 6, 0x0690, 1, 0), + MX7D_PAD_EPDC_SDCE3__LCD_DATA2 = IOMUX_PAD(0x0300, 0x0090, 7, 0x0640, 1, 0), + + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK = IOMUX_PAD(0x0304, 0x0094, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0 = IOMUX_PAD(0x0304, 0x0094, 1, 0x05AC, 0, 0), + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 = IOMUX_PAD(0x0304, 0x0094, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDCLK__KPP_COL7 = IOMUX_PAD(0x0304, 0x0094, 3, 0x0610, 0, 0), + MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 = IOMUX_PAD(0x0304, 0x0094, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 = IOMUX_PAD(0x0304, 0x0094, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDCLK__LCD_DATA23 = IOMUX_PAD(0x0304, 0x0094, 6, 0x0694, 1, 0), + MX7D_PAD_EPDC_GDCLK__LCD_DATA16 = IOMUX_PAD(0x0304, 0x0094, 7, 0x0678, 1, 0), + + MX7D_PAD_EPDC_GDOE__EPDC_GDOE = IOMUX_PAD(0x0308, 0x0098, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1 = IOMUX_PAD(0x0308, 0x0098, 1, 0x05B0, 0, 0), + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 = IOMUX_PAD(0x0308, 0x0098, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__KPP_ROW7 = IOMUX_PAD(0x0308, 0x0098, 3, 0x0630, 0, 0), + MX7D_PAD_EPDC_GDOE__EIM_ADDR19 = IOMUX_PAD(0x0308, 0x0098, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__GPIO2_IO25 = IOMUX_PAD(0x0308, 0x0098, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__LCD_WR_RWN = IOMUX_PAD(0x0308, 0x0098, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__LCD_DATA18 = IOMUX_PAD(0x0308, 0x0098, 7, 0x0680, 1, 0), + + MX7D_PAD_EPDC_GDRL__EPDC_GDRL = IOMUX_PAD(0x030C, 0x009C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2 = IOMUX_PAD(0x030C, 0x009C, 1, 0x05B4, 0, 0), + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL = IOMUX_PAD(0x030C, 0x009C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__EIM_ADDR20 = IOMUX_PAD(0x030C, 0x009C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__GPIO2_IO26 = IOMUX_PAD(0x030C, 0x009C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__LCD_RD_E = IOMUX_PAD(0x030C, 0x009C, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__LCD_DATA19 = IOMUX_PAD(0x030C, 0x009C, 7, 0x0684, 1, 0), + + MX7D_PAD_EPDC_GDSP__EPDC_GDSP = IOMUX_PAD(0x0310, 0x00A0, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3 = IOMUX_PAD(0x0310, 0x00A0, 1, 0x05B8, 0, 0), + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC = IOMUX_PAD(0x0310, 0x00A0, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__ENET2_TX_ER = IOMUX_PAD(0x0310, 0x00A0, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__EIM_ADDR21 = IOMUX_PAD(0x0310, 0x00A0, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__GPIO2_IO27 = IOMUX_PAD(0x0310, 0x00A0, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__LCD_BUSY = IOMUX_PAD(0x0310, 0x00A0, 6, 0x0634, 1, 0), + MX7D_PAD_EPDC_GDSP__LCD_DATA17 = IOMUX_PAD(0x0310, 0x00A0, 7, 0x067C, 1, 0), + + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 = IOMUX_PAD(0x0314, 0x00A4, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK = IOMUX_PAD(0x0314, 0x00A4, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x0314, 0x00A4, 3, 0x0570, 1, 0), + MX7D_PAD_EPDC_BDR0__EIM_ADDR22 = IOMUX_PAD(0x0314, 0x00A4, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 = IOMUX_PAD(0x0314, 0x00A4, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__LCD_CS = IOMUX_PAD(0x0314, 0x00A4, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__LCD_DATA7 = IOMUX_PAD(0x0314, 0x00A4, 7, 0x0654, 1, 0), + + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 = IOMUX_PAD(0x0318, 0x00A8, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN = IOMUX_PAD(0x0318, 0x00A8, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK = IOMUX_PAD(0x0318, 0x00A8, 2, 0x0578, 1, 0), + MX7D_PAD_EPDC_BDR1__EIM_AD8 = IOMUX_PAD(0x0318, 0x00A8, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 = IOMUX_PAD(0x0318, 0x00A8, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__LCD_ENABLE = IOMUX_PAD(0x0318, 0x00A8, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__LCD_DATA6 = IOMUX_PAD(0x0318, 0x00A8, 7, 0x0650, 1, 0), + + MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM = IOMUX_PAD(0x031C, 0x00AC, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA = IOMUX_PAD(0x031C, 0x00AC, 1, 0x05CC, 0, 0), + MX7D_PAD_EPDC_PWR_COM__ENET2_CRS = IOMUX_PAD(0x031C, 0x00AC, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__EIM_AD9 = IOMUX_PAD(0x031C, 0x00AC, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 = IOMUX_PAD(0x031C, 0x00AC, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC = IOMUX_PAD(0x031C, 0x00AC, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__LCD_DATA11 = IOMUX_PAD(0x031C, 0x00AC, 7, 0x0664, 1, 0), + + MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT = IOMUX_PAD(0x0320, 0x00B0, 0, 0x0580, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB = IOMUX_PAD(0x0320, 0x00B0, 1, 0x05D0, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__ENET2_COL = IOMUX_PAD(0x0320, 0x00B0, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1 = IOMUX_PAD(0x0320, 0x00B0, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 = IOMUX_PAD(0x0320, 0x00B0, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC = IOMUX_PAD(0x0320, 0x00B0, 6, 0x0698, 1, 0), + MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12 = IOMUX_PAD(0x0320, 0x00B0, 7, 0x0668, 1, 0), + + MX7D_PAD_LCD_CLK__LCD_CLK = IOMUX_PAD(0x0324, 0x00B4, 0, 0x0000, 0, 0), + MX7D_PAD_LCD_CLK__ECSPI4_MISO = IOMUX_PAD(0x0324, 0x00B4, 1, 0x0558, 0, 0), + MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x0324, 0x00B4, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_CLK__CSI_DATA16 = IOMUX_PAD(0x0324, 0x00B4, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_CLK__UART2_DCE_RX = IOMUX_PAD(0x0324, 0x00B4, 4, 0x06FC, 0, 0), + MX7D_PAD_LCD_CLK__UART2_DTE_TX = IOMUX_PAD(0x0324, 0x00B4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_CLK__GPIO3_IO0 = IOMUX_PAD(0x0324, 0x00B4, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_ENABLE__LCD_ENABLE = IOMUX_PAD(0x0328, 0x00B8, 0, 0x0000, 0, 0), + MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI = IOMUX_PAD(0x0328, 0x00B8, 1, 0x055C, 0, 0), + MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x0328, 0x00B8, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_ENABLE__CSI_DATA17 = IOMUX_PAD(0x0328, 0x00B8, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_ENABLE__UART2_DCE_TX = IOMUX_PAD(0x0328, 0x00B8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_ENABLE__UART2_DTE_RX = IOMUX_PAD(0x0328, 0x00B8, 4, 0x06FC, 1, 0), + MX7D_PAD_LCD_ENABLE__GPIO3_IO1 = IOMUX_PAD(0x0328, 0x00B8, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_HSYNC__LCD_HSYNC = IOMUX_PAD(0x032C, 0x00BC, 0, 0x0000, 0, 0), + MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK = IOMUX_PAD(0x032C, 0x00BC, 1, 0x0554, 0, 0), + MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x032C, 0x00BC, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_HSYNC__CSI_DATA18 = IOMUX_PAD(0x032C, 0x00BC, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS = IOMUX_PAD(0x032C, 0x00BC, 4, 0x06F8, 0, 0), + MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS = IOMUX_PAD(0x032C, 0x00BC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_HSYNC__GPIO3_IO2 = IOMUX_PAD(0x032C, 0x00BC, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_VSYNC__LCD_VSYNC = IOMUX_PAD(0x0330, 0x00C0, 0, 0x0698, 2, 0), + MX7D_PAD_LCD_VSYNC__ECSPI4_SS0 = IOMUX_PAD(0x0330, 0x00C0, 1, 0x0560, 0, 0), + MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x0330, 0x00C0, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_VSYNC__CSI_DATA19 = IOMUX_PAD(0x0330, 0x00C0, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS = IOMUX_PAD(0x0330, 0x00C0, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS = IOMUX_PAD(0x0330, 0x00C0, 4, 0x06F8, 1, 0), + MX7D_PAD_LCD_VSYNC__GPIO3_IO3 = IOMUX_PAD(0x0330, 0x00C0, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_RESET__LCD_RESET = IOMUX_PAD(0x0334, 0x00C4, 0, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__GPT1_COMPARE1 = IOMUX_PAD(0x0334, 0x00C4, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI = IOMUX_PAD(0x0334, 0x00C4, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__CSI_FIELD = IOMUX_PAD(0x0334, 0x00C4, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__EIM_DTACK_B = IOMUX_PAD(0x0334, 0x00C4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__GPIO3_IO4 = IOMUX_PAD(0x0334, 0x00C4, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA00__LCD_DATA0 = IOMUX_PAD(0x0338, 0x00C8, 0, 0x0638, 2, 0), + MX7D_PAD_LCD_DATA00__GPT1_COMPARE2 = IOMUX_PAD(0x0338, 0x00C8, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA00__CSI_DATA20 = IOMUX_PAD(0x0338, 0x00C8, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA00__EIM_DATA0 = IOMUX_PAD(0x0338, 0x00C8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA00__GPIO3_IO5 = IOMUX_PAD(0x0338, 0x00C8, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0 = IOMUX_PAD(0x0338, 0x00C8, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA01__LCD_DATA1 = IOMUX_PAD(0x033C, 0x00CC, 0, 0x063C, 2, 0), + MX7D_PAD_LCD_DATA01__GPT1_COMPARE3 = IOMUX_PAD(0x033C, 0x00CC, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA01__CSI_DATA21 = IOMUX_PAD(0x033C, 0x00CC, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA01__EIM_DATA1 = IOMUX_PAD(0x033C, 0x00CC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA01__GPIO3_IO6 = IOMUX_PAD(0x033C, 0x00CC, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1 = IOMUX_PAD(0x033C, 0x00CC, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA02__LCD_DATA2 = IOMUX_PAD(0x0340, 0x00D0, 0, 0x0640, 2, 0), + MX7D_PAD_LCD_DATA02__GPT1_CLK = IOMUX_PAD(0x0340, 0x00D0, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA02__CSI_DATA22 = IOMUX_PAD(0x0340, 0x00D0, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA02__EIM_DATA2 = IOMUX_PAD(0x0340, 0x00D0, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA02__GPIO3_IO7 = IOMUX_PAD(0x0340, 0x00D0, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2 = IOMUX_PAD(0x0340, 0x00D0, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA03__LCD_DATA3 = IOMUX_PAD(0x0344, 0x00D4, 0, 0x0644, 2, 0), + MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1 = IOMUX_PAD(0x0344, 0x00D4, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA03__CSI_DATA23 = IOMUX_PAD(0x0344, 0x00D4, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA03__EIM_DATA3 = IOMUX_PAD(0x0344, 0x00D4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA03__GPIO3_IO8 = IOMUX_PAD(0x0344, 0x00D4, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3 = IOMUX_PAD(0x0344, 0x00D4, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA04__LCD_DATA4 = IOMUX_PAD(0x0348, 0x00D8, 0, 0x0648, 2, 0), + MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2 = IOMUX_PAD(0x0348, 0x00D8, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA04__CSI_VSYNC = IOMUX_PAD(0x0348, 0x00D8, 3, 0x0520, 0, 0), + MX7D_PAD_LCD_DATA04__EIM_DATA4 = IOMUX_PAD(0x0348, 0x00D8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA04__GPIO3_IO9 = IOMUX_PAD(0x0348, 0x00D8, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4 = IOMUX_PAD(0x0348, 0x00D8, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA05__LCD_DATA5 = IOMUX_PAD(0x034C, 0x00DC, 0, 0x064C, 2, 0), + MX7D_PAD_LCD_DATA05__CSI_HSYNC = IOMUX_PAD(0x034C, 0x00DC, 3, 0x0518, 0, 0), + MX7D_PAD_LCD_DATA05__EIM_DATA5 = IOMUX_PAD(0x034C, 0x00DC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x034C, 0x00DC, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5 = IOMUX_PAD(0x034C, 0x00DC, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA06__LCD_DATA6 = IOMUX_PAD(0x0350, 0x00E0, 0, 0x0650, 2, 0), + MX7D_PAD_LCD_DATA06__CSI_PIXCLK = IOMUX_PAD(0x0350, 0x00E0, 3, 0x051C, 0, 0), + MX7D_PAD_LCD_DATA06__EIM_DATA6 = IOMUX_PAD(0x0350, 0x00E0, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x0350, 0x00E0, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6 = IOMUX_PAD(0x0350, 0x00E0, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA07__LCD_DATA7 = IOMUX_PAD(0x0354, 0x00E4, 0, 0x0654, 2, 0), + MX7D_PAD_LCD_DATA07__CSI_MCLK = IOMUX_PAD(0x0354, 0x00E4, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA07__EIM_DATA7 = IOMUX_PAD(0x0354, 0x00E4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x0354, 0x00E4, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7 = IOMUX_PAD(0x0354, 0x00E4, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA08__LCD_DATA8 = IOMUX_PAD(0x0358, 0x00E8, 0, 0x0658, 2, 0), + MX7D_PAD_LCD_DATA08__CSI_DATA9 = IOMUX_PAD(0x0358, 0x00E8, 3, 0x0514, 0, 0), + MX7D_PAD_LCD_DATA08__EIM_DATA8 = IOMUX_PAD(0x0358, 0x00E8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA08__GPIO3_IO13 = IOMUX_PAD(0x0358, 0x00E8, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8 = IOMUX_PAD(0x0358, 0x00E8, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA09__LCD_DATA9 = IOMUX_PAD(0x035C, 0x00EC, 0, 0x065C, 2, 0), + MX7D_PAD_LCD_DATA09__CSI_DATA8 = IOMUX_PAD(0x035C, 0x00EC, 3, 0x0510, 0, 0), + MX7D_PAD_LCD_DATA09__EIM_DATA9 = IOMUX_PAD(0x035C, 0x00EC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA09__GPIO3_IO14 = IOMUX_PAD(0x035C, 0x00EC, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9 = IOMUX_PAD(0x035C, 0x00EC, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA10__LCD_DATA10 = IOMUX_PAD(0x0360, 0x00F0, 0, 0x0660, 2, 0), + MX7D_PAD_LCD_DATA10__CSI_DATA7 = IOMUX_PAD(0x0360, 0x00F0, 3, 0x050C, 0, 0), + MX7D_PAD_LCD_DATA10__EIM_DATA10 = IOMUX_PAD(0x0360, 0x00F0, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA10__GPIO3_IO15 = IOMUX_PAD(0x0360, 0x00F0, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x0360, 0x00F0, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA11__LCD_DATA11 = IOMUX_PAD(0x0364, 0x00F4, 0, 0x0664, 2, 0), + MX7D_PAD_LCD_DATA11__CSI_DATA6 = IOMUX_PAD(0x0364, 0x00F4, 3, 0x0508, 0, 0), + MX7D_PAD_LCD_DATA11__EIM_DATA11 = IOMUX_PAD(0x0364, 0x00F4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA11__GPIO3_IO16 = IOMUX_PAD(0x0364, 0x00F4, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0364, 0x00F4, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA12__LCD_DATA12 = IOMUX_PAD(0x0368, 0x00F8, 0, 0x0668, 2, 0), + MX7D_PAD_LCD_DATA12__CSI_DATA5 = IOMUX_PAD(0x0368, 0x00F8, 3, 0x0504, 0, 0), + MX7D_PAD_LCD_DATA12__EIM_DATA12 = IOMUX_PAD(0x0368, 0x00F8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA12__GPIO3_IO17 = IOMUX_PAD(0x0368, 0x00F8, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0368, 0x00F8, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA13__LCD_DATA13 = IOMUX_PAD(0x036C, 0x00FC, 0, 0x066C, 1, 0), + MX7D_PAD_LCD_DATA13__CSI_DATA4 = IOMUX_PAD(0x036C, 0x00FC, 3, 0x0500, 0, 0), + MX7D_PAD_LCD_DATA13__EIM_DATA13 = IOMUX_PAD(0x036C, 0x00FC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA13__GPIO3_IO18 = IOMUX_PAD(0x036C, 0x00FC, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x036C, 0x00FC, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA14__LCD_DATA14 = IOMUX_PAD(0x0370, 0x0100, 0, 0x0670, 1, 0), + MX7D_PAD_LCD_DATA14__CSI_DATA3 = IOMUX_PAD(0x0370, 0x0100, 3, 0x04FC, 0, 0), + MX7D_PAD_LCD_DATA14__EIM_DATA14 = IOMUX_PAD(0x0370, 0x0100, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x0370, 0x0100, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x0370, 0x0100, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA15__LCD_DATA15 = IOMUX_PAD(0x0374, 0x0104, 0, 0x0674, 1, 0), + MX7D_PAD_LCD_DATA15__CSI_DATA2 = IOMUX_PAD(0x0374, 0x0104, 3, 0x04F8, 0, 0), + MX7D_PAD_LCD_DATA15__EIM_DATA15 = IOMUX_PAD(0x0374, 0x0104, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x0374, 0x0104, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0374, 0x0104, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA16__LCD_DATA16 = IOMUX_PAD(0x0378, 0x0108, 0, 0x0678, 2, 0), + MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4 = IOMUX_PAD(0x0378, 0x0108, 1, 0x0594, 0, 0), + MX7D_PAD_LCD_DATA16__CSI_DATA1 = IOMUX_PAD(0x0378, 0x0108, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA16__EIM_CRE = IOMUX_PAD(0x0378, 0x0108, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x0378, 0x0108, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16 = IOMUX_PAD(0x0378, 0x0108, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA17__LCD_DATA17 = IOMUX_PAD(0x037C, 0x010C, 0, 0x067C, 2, 0), + MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5 = IOMUX_PAD(0x037C, 0x010C, 1, 0x0598, 0, 0), + MX7D_PAD_LCD_DATA17__CSI_DATA0 = IOMUX_PAD(0x037C, 0x010C, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN = IOMUX_PAD(0x037C, 0x010C, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x037C, 0x010C, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17 = IOMUX_PAD(0x037C, 0x010C, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA18__LCD_DATA18 = IOMUX_PAD(0x0380, 0x0110, 0, 0x0680, 2, 0), + MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6 = IOMUX_PAD(0x0380, 0x0110, 1, 0x059C, 0, 0), + MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO = IOMUX_PAD(0x0380, 0x0110, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA18__CSI_DATA15 = IOMUX_PAD(0x0380, 0x0110, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA18__EIM_CS2_B = IOMUX_PAD(0x0380, 0x0110, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA18__GPIO3_IO23 = IOMUX_PAD(0x0380, 0x0110, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18 = IOMUX_PAD(0x0380, 0x0110, 6, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA19__EIM_CS3_B = IOMUX_PAD(0x0384, 0x0114, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA19__GPIO3_IO24 = IOMUX_PAD(0x0384, 0x0114, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19 = IOMUX_PAD(0x0384, 0x0114, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA19__LCD_DATA19 = IOMUX_PAD(0x0384, 0x0114, 0, 0x0684, 2, 0), + MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7 = IOMUX_PAD(0x0384, 0x0114, 1, 0x05A0, 0, 0), + MX7D_PAD_LCD_DATA19__CSI_DATA14 = IOMUX_PAD(0x0384, 0x0114, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA20__EIM_ADDR23 = IOMUX_PAD(0x0388, 0x0118, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA20__GPIO3_IO25 = IOMUX_PAD(0x0388, 0x0118, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA20__I2C3_SCL = IOMUX_PAD(0x0388, 0x0118, IOMUX_CONFIG_SION | 6, 0x05E4, 1, 0), + + MX7D_PAD_LCD_DATA20__LCD_DATA20 = IOMUX_PAD(0x0388, 0x0118, 0, 0x0688, 2, 0), + MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4 = IOMUX_PAD(0x0388, 0x0118, 1, 0x05BC, 0, 0), + MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x0388, 0x0118, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA20__CSI_DATA13 = IOMUX_PAD(0x0388, 0x0118, 3, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA21__LCD_DATA21 = IOMUX_PAD(0x038C, 0x011C, 0, 0x068C, 2, 0), + MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5 = IOMUX_PAD(0x038C, 0x011C, 1, 0x05C0, 0, 0), + MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x038C, 0x011C, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA21__CSI_DATA12 = IOMUX_PAD(0x038C, 0x011C, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA21__EIM_ADDR24 = IOMUX_PAD(0x038C, 0x011C, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x038C, 0x011C, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA21__I2C3_SDA = IOMUX_PAD(0x038C, 0x011C, IOMUX_CONFIG_SION | 6, 0x05E8, 1, 0), + + MX7D_PAD_LCD_DATA22__LCD_DATA22 = IOMUX_PAD(0x0390, 0x0120, 0, 0x0690, 2, 0), + MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6 = IOMUX_PAD(0x0390, 0x0120, 1, 0x05C4, 0, 0), + MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x0390, 0x0120, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA22__CSI_DATA11 = IOMUX_PAD(0x0390, 0x0120, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA22__EIM_ADDR25 = IOMUX_PAD(0x0390, 0x0120, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA22__GPIO3_IO27 = IOMUX_PAD(0x0390, 0x0120, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA22__I2C4_SCL = IOMUX_PAD(0x0390, 0x0120, IOMUX_CONFIG_SION | 6, 0x05EC, 1, 0), + + MX7D_PAD_LCD_DATA23__LCD_DATA23 = IOMUX_PAD(0x0394, 0x0124, 0, 0x0694, 2, 0), + MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7 = IOMUX_PAD(0x0394, 0x0124, 1, 0x05C8, 0, 0), + MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x0394, 0x0124, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA23__CSI_DATA10 = IOMUX_PAD(0x0394, 0x0124, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA23__EIM_ADDR26 = IOMUX_PAD(0x0394, 0x0124, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA23__GPIO3_IO28 = IOMUX_PAD(0x0394, 0x0124, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA23__I2C4_SDA = IOMUX_PAD(0x0394, 0x0124, IOMUX_CONFIG_SION | 6, 0x05F0, 1, 0), + + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0), + + MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__I2C1_SCL = IOMUX_PAD(0x0398, 0x0128, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY = IOMUX_PAD(0x0398, 0x0128, 2, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 = IOMUX_PAD(0x0398, 0x0128, 3, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x0398, 0x0128, 4, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 = IOMUX_PAD(0x0398, 0x0128, 5, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__ENET1_MDIO = IOMUX_PAD(0x0398, 0x0128, 6, 0x0000, 0, 0), + + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX = IOMUX_PAD(0x039C, 0x012C, 0, 0x0000, 0, 0), + + MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX = IOMUX_PAD(0x039C, 0x012C, 0, 0x06F4, 1, 0), + MX7D_PAD_UART1_TX_DATA__I2C1_SDA = IOMUX_PAD(0x039C, 0x012C, IOMUX_CONFIG_SION | 1, 0x05D8, 0, 0), + MX7D_PAD_UART1_TX_DATA__SAI3_MCLK = IOMUX_PAD(0x039C, 0x012C, 2, 0x0000, 0, 0), + MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2 = IOMUX_PAD(0x039C, 0x012C, 3, 0x0000, 0, 0), + MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x039C, 0x012C, 4, 0x0000, 0, 0), + MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 = IOMUX_PAD(0x039C, 0x012C, 5, 0x0000, 0, 0), + MX7D_PAD_UART1_TX_DATA__ENET1_MDC = IOMUX_PAD(0x039C, 0x012C, 6, 0x0000, 0, 0), + + MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0), + + MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__I2C2_SCL = IOMUX_PAD(0x03A0, 0x0130, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK = IOMUX_PAD(0x03A0, 0x0130, 2, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 = IOMUX_PAD(0x03A0, 0x0130, 3, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x03A0, 0x0130, 4, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 = IOMUX_PAD(0x03A0, 0x0130, 5, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__ENET2_MDIO = IOMUX_PAD(0x03A0, 0x0130, 6, 0x0000, 0, 0), + + MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0), + + MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0), + MX7D_PAD_UART2_TX_DATA__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0134, IOMUX_CONFIG_SION | 1, 0x05E0, 0, 0), + MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 = IOMUX_PAD(0x03A4, 0x0134, 2, 0x06C8, 0, 0), + MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY = IOMUX_PAD(0x03A4, 0x0134, 3, 0x0000, 0, 0), + MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x03A4, 0x0134, 4, 0x0000, 0, 0), + MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 = IOMUX_PAD(0x03A4, 0x0134, 5, 0x0000, 0, 0), + MX7D_PAD_UART2_TX_DATA__ENET2_MDC = IOMUX_PAD(0x03A4, 0x0134, 6, 0x0000, 0, 0), + + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX = IOMUX_PAD(0x03A8, 0x0138, 0, 0x0704, 2, 0), + + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX = IOMUX_PAD(0x03A8, 0x0138, 0, 0x0000, 0, 0), + MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC = IOMUX_PAD(0x03A8, 0x0138, 1, 0x072C, 0, 0), + MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC = IOMUX_PAD(0x03A8, 0x0138, 2, 0x06CC, 0, 0), + MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0138, 3, 0x0528, 0, 0), + MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x03A8, 0x0138, 4, 0x0000, 0, 0), + MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 = IOMUX_PAD(0x03A8, 0x0138, 5, 0x0000, 0, 0), + MX7D_PAD_UART3_RX_DATA__SD1_LCTL = IOMUX_PAD(0x03A8, 0x0138, 6, 0x0000, 0, 0), + + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX = IOMUX_PAD(0x03AC, 0x013C, 0, 0x0000, 0, 0), + + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX = IOMUX_PAD(0x03AC, 0x013C, 0, 0x0704, 3, 0), + MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR = IOMUX_PAD(0x03AC, 0x013C, 1, 0x0000, 0, 0), + MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK = IOMUX_PAD(0x03AC, 0x013C, 2, 0x06D0, 0, 0), + MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x013C, 3, 0x052C, 0, 0), + MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x03AC, 0x013C, 4, 0x0000, 0, 0), + MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 = IOMUX_PAD(0x03AC, 0x013C, 5, 0x0000, 0, 0), + MX7D_PAD_UART3_TX_DATA__SD2_LCTL = IOMUX_PAD(0x03AC, 0x013C, 6, 0x0000, 0, 0), + + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0), + + MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__USB_OTG2_OC = IOMUX_PAD(0x03B0, 0x0140, 1, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 = IOMUX_PAD(0x03B0, 0x0140, 2, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK = IOMUX_PAD(0x03B0, 0x0140, 3, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x03B0, 0x0140, 4, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__GPIO4_IO6 = IOMUX_PAD(0x03B0, 0x0140, 5, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__SD3_LCTL = IOMUX_PAD(0x03B0, 0x0140, 6, 0x0000, 0, 0), + + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS = IOMUX_PAD(0x03B4, 0x0144, 0, 0x0000, 0, 0), + + MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS = IOMUX_PAD(0x03B4, 0x0144, 0, 0x0700, 3, 0), + MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR = IOMUX_PAD(0x03B4, 0x0144, 1, 0x0000, 0, 0), + MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC = IOMUX_PAD(0x03B4, 0x0144, 2, 0x06D4, 0, 0), + MX7D_PAD_UART3_CTS_B__ECSPI1_SS0 = IOMUX_PAD(0x03B4, 0x0144, 3, 0x0530, 0, 0), + MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x03B4, 0x0144, 4, 0x0000, 0, 0), + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 = IOMUX_PAD(0x03B4, 0x0144, 5, 0x0000, 0, 0), + MX7D_PAD_UART3_CTS_B__SD1_VSELECT = IOMUX_PAD(0x03B4, 0x0144, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x03B8, 0x0148, IOMUX_CONFIG_SION | 0, 0x05D4, 1, 0), + MX7D_PAD_I2C1_SCL__UART4_DCE_CTS = IOMUX_PAD(0x03B8, 0x0148, 1, 0x0000, 0, 0), + MX7D_PAD_I2C1_SCL__UART4_DTE_RTS = IOMUX_PAD(0x03B8, 0x0148, 1, 0x0708, 0, 0), + MX7D_PAD_I2C1_SCL__FLEXCAN1_RX = IOMUX_PAD(0x03B8, 0x0148, 2, 0x04DC, 1, 0), + MX7D_PAD_I2C1_SCL__ECSPI3_MISO = IOMUX_PAD(0x03B8, 0x0148, 3, 0x0548, 0, 0), + MX7D_PAD_I2C1_SCL__GPIO4_IO8 = IOMUX_PAD(0x03B8, 0x0148, 5, 0x0000, 0, 0), + MX7D_PAD_I2C1_SCL__SD2_VSELECT = IOMUX_PAD(0x03B8, 0x0148, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x03BC, 0x014C, IOMUX_CONFIG_SION | 0, 0x05D8, 1, 0), + MX7D_PAD_I2C1_SDA__UART4_DCE_RTS = IOMUX_PAD(0x03BC, 0x014C, 1, 0x0708, 1, 0), + MX7D_PAD_I2C1_SDA__UART4_DTE_CTS = IOMUX_PAD(0x03BC, 0x014C, 1, 0x0000, 0, 0), + MX7D_PAD_I2C1_SDA__FLEXCAN1_TX = IOMUX_PAD(0x03BC, 0x014C, 2, 0x0000, 0, 0), + MX7D_PAD_I2C1_SDA__ECSPI3_MOSI = IOMUX_PAD(0x03BC, 0x014C, 3, 0x054C, 0, 0), + MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x03BC, 0x014C, 4, 0x0564, 1, 0), + MX7D_PAD_I2C1_SDA__GPIO4_IO9 = IOMUX_PAD(0x03BC, 0x014C, 5, 0x0000, 0, 0), + MX7D_PAD_I2C1_SDA__SD3_VSELECT = IOMUX_PAD(0x03BC, 0x014C, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x03C0, 0x0150, IOMUX_CONFIG_SION | 0, 0x05DC, 1, 0), + MX7D_PAD_I2C2_SCL__UART4_DCE_RX = IOMUX_PAD(0x03C0, 0x0150, 1, 0x070C, 0, 0), + MX7D_PAD_I2C2_SCL__UART4_DTE_TX = IOMUX_PAD(0x03C0, 0x0150, 1, 0x0000, 0, 0), + MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B = IOMUX_PAD(0x03C0, 0x0150, 2, 0x0000, 0, 0), + MX7D_PAD_I2C2_SCL__ECSPI3_SCLK = IOMUX_PAD(0x03C0, 0x0150, 3, 0x0544, 0, 0), + MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x03C0, 0x0150, 4, 0x0570, 2, 0), + MX7D_PAD_I2C2_SCL__GPIO4_IO10 = IOMUX_PAD(0x03C0, 0x0150, 5, 0x0000, 0, 0), + MX7D_PAD_I2C2_SCL__SD3_CD_B = IOMUX_PAD(0x03C0, 0x0150, 6, 0x0738, 1, 0), + + MX7D_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x03C4, 0x0154, IOMUX_CONFIG_SION | 0, 0x05E0, 1, 0), + MX7D_PAD_I2C2_SDA__UART4_DCE_TX = IOMUX_PAD(0x03C4, 0x0154, 1, 0x0000, 0, 0), + MX7D_PAD_I2C2_SDA__UART4_DTE_RX = IOMUX_PAD(0x03C4, 0x0154, 1, 0x070C, 1, 0), + MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x03C4, 0x0154, 2, 0x0000, 0, 0), + MX7D_PAD_I2C2_SDA__ECSPI3_SS0 = IOMUX_PAD(0x03C4, 0x0154, 3, 0x0550, 0, 0), + MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x03C4, 0x0154, 4, 0x0000, 0, 0), + MX7D_PAD_I2C2_SDA__GPIO4_IO11 = IOMUX_PAD(0x03C4, 0x0154, 5, 0x0000, 0, 0), + MX7D_PAD_I2C2_SDA__SD3_WP = IOMUX_PAD(0x03C4, 0x0154, 6, 0x073C, 1, 0), + + MX7D_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x03C8, 0x0158, IOMUX_CONFIG_SION | 0, 0x05E4, 2, 0), + MX7D_PAD_I2C3_SCL__UART5_DCE_CTS = IOMUX_PAD(0x03C8, 0x0158, 1, 0x0000, 0, 0), + MX7D_PAD_I2C3_SCL__UART5_DTE_RTS = IOMUX_PAD(0x03C8, 0x0158, 1, 0x0710, 0, 0), + MX7D_PAD_I2C3_SCL__FLEXCAN2_RX = IOMUX_PAD(0x03C8, 0x0158, 2, 0x04E0, 1, 0), + MX7D_PAD_I2C3_SCL__CSI_VSYNC = IOMUX_PAD(0x03C8, 0x0158, 3, 0x0520, 1, 0), + MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0 = IOMUX_PAD(0x03C8, 0x0158, 4, 0x06D8, 1, 0), + MX7D_PAD_I2C3_SCL__GPIO4_IO12 = IOMUX_PAD(0x03C8, 0x0158, 5, 0x0000, 0, 0), + MX7D_PAD_I2C3_SCL__EPDC_BDR0 = IOMUX_PAD(0x03C8, 0x0158, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x03CC, 0x015C, IOMUX_CONFIG_SION | 0, 0x05E8, 2, 0), + MX7D_PAD_I2C3_SDA__UART5_DCE_RTS = IOMUX_PAD(0x03CC, 0x015C, 1, 0x0710, 1, 0), + MX7D_PAD_I2C3_SDA__UART5_DTE_CTS = IOMUX_PAD(0x03CC, 0x015C, 1, 0x0000, 0, 0), + MX7D_PAD_I2C3_SDA__FLEXCAN2_TX = IOMUX_PAD(0x03CC, 0x015C, 2, 0x0000, 0, 0), + MX7D_PAD_I2C3_SDA__CSI_HSYNC = IOMUX_PAD(0x03CC, 0x015C, 3, 0x0518, 1, 0), + MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1 = IOMUX_PAD(0x03CC, 0x015C, 4, 0x06DC, 1, 0), + MX7D_PAD_I2C3_SDA__GPIO4_IO13 = IOMUX_PAD(0x03CC, 0x015C, 5, 0x0000, 0, 0), + MX7D_PAD_I2C3_SDA__EPDC_BDR1 = IOMUX_PAD(0x03CC, 0x015C, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x03D0, 0x0160, IOMUX_CONFIG_SION | 0, 0x05EC, 2, 0), + MX7D_PAD_I2C4_SCL__UART5_DCE_RX = IOMUX_PAD(0x03D0, 0x0160, 1, 0x0714, 0, 0), + MX7D_PAD_I2C4_SCL__UART5_DTE_TX = IOMUX_PAD(0x03D0, 0x0160, 1, 0x0000, 0, 0), + MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B = IOMUX_PAD(0x03D0, 0x0160, 2, 0x0000, 0, 0), + MX7D_PAD_I2C4_SCL__CSI_PIXCLK = IOMUX_PAD(0x03D0, 0x0160, 3, 0x051C, 1, 0), + MX7D_PAD_I2C4_SCL__USB_OTG1_ID = IOMUX_PAD(0x03D0, 0x0160, 4, 0x0734, 1, 0), + MX7D_PAD_I2C4_SCL__GPIO4_IO14 = IOMUX_PAD(0x03D0, 0x0160, 5, 0x0000, 0, 0), + MX7D_PAD_I2C4_SCL__EPDC_VCOM0 = IOMUX_PAD(0x03D0, 0x0160, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x03D4, 0x0164, IOMUX_CONFIG_SION | 0, 0x05F0, 2, 0), + MX7D_PAD_I2C4_SDA__UART5_DCE_TX = IOMUX_PAD(0x03D4, 0x0164, 1, 0x0000, 0, 0), + MX7D_PAD_I2C4_SDA__UART5_DTE_RX = IOMUX_PAD(0x03D4, 0x0164, 1, 0x0714, 1, 0), + MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB = IOMUX_PAD(0x03D4, 0x0164, 2, 0x0000, 0, 0), + MX7D_PAD_I2C4_SDA__CSI_MCLK = IOMUX_PAD(0x03D4, 0x0164, 3, 0x0000, 0, 0), + MX7D_PAD_I2C4_SDA__USB_OTG2_ID = IOMUX_PAD(0x03D4, 0x0164, 4, 0x0730, 1, 0), + MX7D_PAD_I2C4_SDA__GPIO4_IO15 = IOMUX_PAD(0x03D4, 0x0164, 5, 0x0000, 0, 0), + MX7D_PAD_I2C4_SDA__EPDC_VCOM1 = IOMUX_PAD(0x03D4, 0x0164, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x03D8, 0x0168, 0, 0x0524, 1, 0), + MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX = IOMUX_PAD(0x03D8, 0x0168, 1, 0x071C, 2, 0), + MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX = IOMUX_PAD(0x03D8, 0x0168, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 = IOMUX_PAD(0x03D8, 0x0168, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SCLK__CSI_DATA2 = IOMUX_PAD(0x03D8, 0x0168, 3, 0x04F8, 1, 0), + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 = IOMUX_PAD(0x03D8, 0x0168, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM = IOMUX_PAD(0x03D8, 0x0168, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x03DC, 0x016C, 0, 0x052C, 1, 0), + MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX = IOMUX_PAD(0x03DC, 0x016C, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX = IOMUX_PAD(0x03DC, 0x016C, 1, 0x071C, 3, 0), + MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 = IOMUX_PAD(0x03DC, 0x016C, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MOSI__CSI_DATA3 = IOMUX_PAD(0x03DC, 0x016C, 3, 0x04FC, 1, 0), + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 = IOMUX_PAD(0x03DC, 0x016C, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT = IOMUX_PAD(0x03DC, 0x016C, 6, 0x0580, 1, 0), + + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x03E0, 0x0170, 0, 0x0528, 1, 0), + MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS = IOMUX_PAD(0x03E0, 0x0170, 1, 0x0718, 2, 0), + MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS = IOMUX_PAD(0x03E0, 0x0170, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MISO__SD2_DATA6 = IOMUX_PAD(0x03E0, 0x0170, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MISO__CSI_DATA4 = IOMUX_PAD(0x03E0, 0x0170, 3, 0x0500, 1, 0), + MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 = IOMUX_PAD(0x03E0, 0x0170, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ = IOMUX_PAD(0x03E0, 0x0170, 6, 0x057C, 0, 0), + + MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x03E4, 0x0174, 0, 0x0530, 1, 0), + MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS = IOMUX_PAD(0x03E4, 0x0174, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS = IOMUX_PAD(0x03E4, 0x0174, 1, 0x0718, 3, 0), + MX7D_PAD_ECSPI1_SS0__SD2_DATA7 = IOMUX_PAD(0x03E4, 0x0174, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SS0__CSI_DATA5 = IOMUX_PAD(0x03E4, 0x0174, 3, 0x0504, 1, 0), + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 = IOMUX_PAD(0x03E4, 0x0174, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3 = IOMUX_PAD(0x03E4, 0x0174, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x03E8, 0x0178, 0, 0x0534, 0, 0), + MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x0178, 1, 0x0724, 2, 0), + MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX = IOMUX_PAD(0x03E8, 0x0178, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 = IOMUX_PAD(0x03E8, 0x0178, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SCLK__CSI_DATA6 = IOMUX_PAD(0x03E8, 0x0178, 3, 0x0508, 1, 0), + MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 = IOMUX_PAD(0x03E8, 0x0178, 4, 0x066C, 2, 0), + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 = IOMUX_PAD(0x03E8, 0x0178, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0 = IOMUX_PAD(0x03E8, 0x0178, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x03EC, 0x017C, 0, 0x053C, 0, 0), + MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX = IOMUX_PAD(0x03EC, 0x017C, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX = IOMUX_PAD(0x03EC, 0x017C, 1, 0x0724, 3, 0), + MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 = IOMUX_PAD(0x03EC, 0x017C, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MOSI__CSI_DATA7 = IOMUX_PAD(0x03EC, 0x017C, 3, 0x050C, 1, 0), + MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 = IOMUX_PAD(0x03EC, 0x017C, 4, 0x0670, 2, 0), + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 = IOMUX_PAD(0x03EC, 0x017C, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1 = IOMUX_PAD(0x03EC, 0x017C, 6, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 = IOMUX_PAD(0x03F0, 0x0180, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2 = IOMUX_PAD(0x03F0, 0x0180, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x03F0, 0x0180, 0, 0x0538, 0, 0), + MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS = IOMUX_PAD(0x03F0, 0x0180, 1, 0x0720, 2, 0), + MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS = IOMUX_PAD(0x03F0, 0x0180, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MISO__SD1_DATA6 = IOMUX_PAD(0x03F0, 0x0180, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MISO__CSI_DATA8 = IOMUX_PAD(0x03F0, 0x0180, 3, 0x0510, 1, 0), + MX7D_PAD_ECSPI2_MISO__LCD_DATA15 = IOMUX_PAD(0x03F0, 0x0180, 4, 0x0674, 2, 0), + + MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x03F4, 0x0184, 0, 0x0540, 0, 0), + MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS = IOMUX_PAD(0x03F4, 0x0184, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS = IOMUX_PAD(0x03F4, 0x0184, 1, 0x0720, 3, 0), + MX7D_PAD_ECSPI2_SS0__SD1_DATA7 = IOMUX_PAD(0x03F4, 0x0184, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SS0__CSI_DATA9 = IOMUX_PAD(0x03F4, 0x0184, 3, 0x0514, 1, 0), + MX7D_PAD_ECSPI2_SS0__LCD_RESET = IOMUX_PAD(0x03F4, 0x0184, 4, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 = IOMUX_PAD(0x03F4, 0x0184, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE = IOMUX_PAD(0x03F4, 0x0184, 6, 0x0000, 0, 0), + + MX7D_PAD_SD1_CD_B__SD1_CD_B = IOMUX_PAD(0x03F8, 0x0188, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_CD_B__UART6_DCE_RX = IOMUX_PAD(0x03F8, 0x0188, 2, 0x071C, 4, 0), + MX7D_PAD_SD1_CD_B__UART6_DTE_TX = IOMUX_PAD(0x03F8, 0x0188, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_CD_B__ECSPI4_MISO = IOMUX_PAD(0x03F8, 0x0188, 3, 0x0558, 1, 0), + MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0 = IOMUX_PAD(0x03F8, 0x0188, 4, 0x0584, 1, 0), + MX7D_PAD_SD1_CD_B__GPIO5_IO0 = IOMUX_PAD(0x03F8, 0x0188, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_CD_B__CCM_CLKO1 = IOMUX_PAD(0x03F8, 0x0188, 6, 0x0000, 0, 0), + + MX7D_PAD_SD1_WP__SD1_WP = IOMUX_PAD(0x03FC, 0x018C, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_WP__UART6_DCE_TX = IOMUX_PAD(0x03FC, 0x018C, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_WP__UART6_DTE_RX = IOMUX_PAD(0x03FC, 0x018C, 2, 0x071C, 5, 0), + MX7D_PAD_SD1_WP__ECSPI4_MOSI = IOMUX_PAD(0x03FC, 0x018C, 3, 0x055C, 1, 0), + MX7D_PAD_SD1_WP__FLEXTIMER1_CH1 = IOMUX_PAD(0x03FC, 0x018C, 4, 0x0588, 1, 0), + MX7D_PAD_SD1_WP__GPIO5_IO1 = IOMUX_PAD(0x03FC, 0x018C, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_WP__CCM_CLKO2 = IOMUX_PAD(0x03FC, 0x018C, 6, 0x0000, 0, 0), + + MX7D_PAD_SD1_RESET_B__SD1_RESET_B = IOMUX_PAD(0x0400, 0x0190, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_RESET_B__SAI3_MCLK = IOMUX_PAD(0x0400, 0x0190, 1, 0x0000, 0, 0), + MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS = IOMUX_PAD(0x0400, 0x0190, 2, 0x0718, 4, 0), + MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS = IOMUX_PAD(0x0400, 0x0190, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK = IOMUX_PAD(0x0400, 0x0190, 3, 0x0554, 1, 0), + MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2 = IOMUX_PAD(0x0400, 0x0190, 4, 0x058C, 1, 0), + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 = IOMUX_PAD(0x0400, 0x0190, 5, 0x0000, 0, 0), + + MX7D_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x0404, 0x0194, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_CLK__SAI3_RX_SYNC = IOMUX_PAD(0x0404, 0x0194, 1, 0x06CC, 1, 0), + MX7D_PAD_SD1_CLK__UART6_DCE_CTS = IOMUX_PAD(0x0404, 0x0194, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_CLK__UART6_DTE_RTS = IOMUX_PAD(0x0404, 0x0194, 2, 0x0718, 5, 0), + MX7D_PAD_SD1_CLK__ECSPI4_SS0 = IOMUX_PAD(0x0404, 0x0194, 3, 0x0560, 1, 0), + MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3 = IOMUX_PAD(0x0404, 0x0194, 4, 0x0590, 1, 0), + MX7D_PAD_SD1_CLK__GPIO5_IO3 = IOMUX_PAD(0x0404, 0x0194, 5, 0x0000, 0, 0), + + MX7D_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x0408, 0x0198, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_CMD__SAI3_RX_BCLK = IOMUX_PAD(0x0408, 0x0198, 1, 0x06C4, 1, 0), + MX7D_PAD_SD1_CMD__ECSPI4_SS1 = IOMUX_PAD(0x0408, 0x0198, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0 = IOMUX_PAD(0x0408, 0x0198, 4, 0x05AC, 1, 0), + MX7D_PAD_SD1_CMD__GPIO5_IO4 = IOMUX_PAD(0x0408, 0x0198, 5, 0x0000, 0, 0), + + MX7D_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x040C, 0x019C, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0 = IOMUX_PAD(0x040C, 0x019C, 1, 0x06C8, 1, 0), + MX7D_PAD_SD1_DATA0__UART7_DCE_RX = IOMUX_PAD(0x040C, 0x019C, 2, 0x0724, 4, 0), + MX7D_PAD_SD1_DATA0__UART7_DTE_TX = IOMUX_PAD(0x040C, 0x019C, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA0__ECSPI4_SS2 = IOMUX_PAD(0x040C, 0x019C, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1 = IOMUX_PAD(0x040C, 0x019C, 4, 0x05B0, 1, 0), + MX7D_PAD_SD1_DATA0__GPIO5_IO5 = IOMUX_PAD(0x040C, 0x019C, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1 = IOMUX_PAD(0x040C, 0x019C, 6, 0x04E4, 1, 0), + + MX7D_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x0410, 0x01A0, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK = IOMUX_PAD(0x0410, 0x01A0, 1, 0x06D0, 1, 0), + MX7D_PAD_SD1_DATA1__UART7_DCE_TX = IOMUX_PAD(0x0410, 0x01A0, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA1__UART7_DTE_RX = IOMUX_PAD(0x0410, 0x01A0, 2, 0x0724, 5, 0), + MX7D_PAD_SD1_DATA1__ECSPI4_SS3 = IOMUX_PAD(0x0410, 0x01A0, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2 = IOMUX_PAD(0x0410, 0x01A0, 4, 0x05B4, 1, 0), + MX7D_PAD_SD1_DATA1__GPIO5_IO6 = IOMUX_PAD(0x0410, 0x01A0, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2 = IOMUX_PAD(0x0410, 0x01A0, 6, 0x04E8, 1, 0), + + MX7D_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x0414, 0x01A4, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC = IOMUX_PAD(0x0414, 0x01A4, 1, 0x06D4, 1, 0), + MX7D_PAD_SD1_DATA2__UART7_DCE_CTS = IOMUX_PAD(0x0414, 0x01A4, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA2__UART7_DTE_RTS = IOMUX_PAD(0x0414, 0x01A4, 2, 0x0720, 4, 0), + MX7D_PAD_SD1_DATA2__ECSPI4_RDY = IOMUX_PAD(0x0414, 0x01A4, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3 = IOMUX_PAD(0x0414, 0x01A4, 4, 0x05B8, 1, 0), + MX7D_PAD_SD1_DATA2__GPIO5_IO7 = IOMUX_PAD(0x0414, 0x01A4, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3 = IOMUX_PAD(0x0414, 0x01A4, 6, 0x04EC, 1, 0), + + MX7D_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x0418, 0x01A8, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 = IOMUX_PAD(0x0418, 0x01A8, 1, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__UART7_DCE_RTS = IOMUX_PAD(0x0418, 0x01A8, 2, 0x0720, 5, 0), + MX7D_PAD_SD1_DATA3__UART7_DTE_CTS = IOMUX_PAD(0x0418, 0x01A8, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__ECSPI3_SS1 = IOMUX_PAD(0x0418, 0x01A8, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA = IOMUX_PAD(0x0418, 0x01A8, 4, 0x05A4, 1, 0), + MX7D_PAD_SD1_DATA3__GPIO5_IO8 = IOMUX_PAD(0x0418, 0x01A8, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4 = IOMUX_PAD(0x0418, 0x01A8, 6, 0x04F0, 1, 0), + + MX7D_PAD_SD2_CD_B__SD2_CD_B = IOMUX_PAD(0x041C, 0x01AC, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_CD_B__ENET1_MDIO = IOMUX_PAD(0x041C, 0x01AC, 1, 0x0568, 2, 0), + MX7D_PAD_SD2_CD_B__ENET2_MDIO = IOMUX_PAD(0x041C, 0x01AC, 2, 0x0574, 2, 0), + MX7D_PAD_SD2_CD_B__ECSPI3_SS2 = IOMUX_PAD(0x041C, 0x01AC, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB = IOMUX_PAD(0x041C, 0x01AC, 4, 0x05A8, 1, 0), + MX7D_PAD_SD2_CD_B__GPIO5_IO9 = IOMUX_PAD(0x041C, 0x01AC, 5, 0x0000, 0, 0), + MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 = IOMUX_PAD(0x041C, 0x01AC, 6, 0x06D8, 2, 0), + + MX7D_PAD_SD2_WP__SD2_WP = IOMUX_PAD(0x0420, 0x01B0, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__ENET1_MDC = IOMUX_PAD(0x0420, 0x01B0, 1, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__ENET2_MDC = IOMUX_PAD(0x0420, 0x01B0, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__ECSPI3_SS3 = IOMUX_PAD(0x0420, 0x01B0, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__USB_OTG1_ID = IOMUX_PAD(0x0420, 0x01B0, 4, 0x0734, 2, 0), + MX7D_PAD_SD2_WP__GPIO5_IO10 = IOMUX_PAD(0x0420, 0x01B0, 5, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0420, 0x01B0, 6, 0x06DC, 2, 0), + + MX7D_PAD_SD2_RESET_B__SD2_RESET_B = IOMUX_PAD(0x0424, 0x01B4, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_RESET_B__SAI2_MCLK = IOMUX_PAD(0x0424, 0x01B4, 1, 0x0000, 0, 0), + MX7D_PAD_SD2_RESET_B__SD2_RESET = IOMUX_PAD(0x0424, 0x01B4, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_RESET_B__ECSPI3_RDY = IOMUX_PAD(0x0424, 0x01B4, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_RESET_B__USB_OTG2_ID = IOMUX_PAD(0x0424, 0x01B4, 4, 0x0730, 2, 0), + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 = IOMUX_PAD(0x0424, 0x01B4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x0428, 0x01B8, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_CLK__SAI2_RX_SYNC = IOMUX_PAD(0x0428, 0x01B8, 1, 0x06B8, 0, 0), + MX7D_PAD_SD2_CLK__MQS_RIGHT = IOMUX_PAD(0x0428, 0x01B8, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_CLK__GPT4_CLK = IOMUX_PAD(0x0428, 0x01B8, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_CLK__GPIO5_IO12 = IOMUX_PAD(0x0428, 0x01B8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x042C, 0x01BC, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_CMD__SAI2_RX_BCLK = IOMUX_PAD(0x042C, 0x01BC, 1, 0x06B0, 0, 0), + MX7D_PAD_SD2_CMD__MQS_LEFT = IOMUX_PAD(0x042C, 0x01BC, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_CMD__GPT4_CAPTURE1 = IOMUX_PAD(0x042C, 0x01BC, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD = IOMUX_PAD(0x042C, 0x01BC, 4, 0x06EC, 1, 0), + MX7D_PAD_SD2_CMD__GPIO5_IO13 = IOMUX_PAD(0x042C, 0x01BC, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x0430, 0x01C0, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0 = IOMUX_PAD(0x0430, 0x01C0, 1, 0x06B4, 0, 0), + MX7D_PAD_SD2_DATA0__UART4_DCE_RX = IOMUX_PAD(0x0430, 0x01C0, 2, 0x070C, 2, 0), + MX7D_PAD_SD2_DATA0__UART4_DTE_TX = IOMUX_PAD(0x0430, 0x01C0, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2 = IOMUX_PAD(0x0430, 0x01C0, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK = IOMUX_PAD(0x0430, 0x01C0, 4, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA0__GPIO5_IO14 = IOMUX_PAD(0x0430, 0x01C0, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x0434, 0x01C4, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK = IOMUX_PAD(0x0434, 0x01C4, 1, 0x06BC, 0, 0), + MX7D_PAD_SD2_DATA1__UART4_DCE_TX = IOMUX_PAD(0x0434, 0x01C4, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA1__UART4_DTE_RX = IOMUX_PAD(0x0434, 0x01C4, 2, 0x070C, 3, 0), + MX7D_PAD_SD2_DATA1__GPT4_COMPARE1 = IOMUX_PAD(0x0434, 0x01C4, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B = IOMUX_PAD(0x0434, 0x01C4, 4, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA1__GPIO5_IO15 = IOMUX_PAD(0x0434, 0x01C4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x0438, 0x01C8, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC = IOMUX_PAD(0x0438, 0x01C8, 1, 0x06C0, 0, 0), + MX7D_PAD_SD2_DATA2__UART4_DCE_CTS = IOMUX_PAD(0x0438, 0x01C8, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA2__UART4_DTE_RTS = IOMUX_PAD(0x0438, 0x01C8, 2, 0x0708, 2, 0), + MX7D_PAD_SD2_DATA2__GPT4_COMPARE2 = IOMUX_PAD(0x0438, 0x01C8, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN = IOMUX_PAD(0x0438, 0x01C8, 4, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA2__GPIO5_IO16 = IOMUX_PAD(0x0438, 0x01C8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x043C, 0x01CC, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0 = IOMUX_PAD(0x043C, 0x01CC, 1, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA3__UART4_DCE_RTS = IOMUX_PAD(0x043C, 0x01CC, 2, 0x0708, 3, 0), + MX7D_PAD_SD2_DATA3__UART4_DTE_CTS = IOMUX_PAD(0x043C, 0x01CC, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA3__GPT4_COMPARE3 = IOMUX_PAD(0x043C, 0x01CC, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD = IOMUX_PAD(0x043C, 0x01CC, 4, 0x06E8, 1, 0), + MX7D_PAD_SD2_DATA3__GPIO5_IO17 = IOMUX_PAD(0x043C, 0x01CC, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x0440, 0x01D0, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_CLK__NAND_CLE = IOMUX_PAD(0x0440, 0x01D0, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_CLK__ECSPI4_MISO = IOMUX_PAD(0x0440, 0x01D0, 2, 0x0558, 2, 0), + MX7D_PAD_SD3_CLK__SAI3_RX_SYNC = IOMUX_PAD(0x0440, 0x01D0, 3, 0x06CC, 2, 0), + MX7D_PAD_SD3_CLK__GPT3_CLK = IOMUX_PAD(0x0440, 0x01D0, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_CLK__GPIO6_IO0 = IOMUX_PAD(0x0440, 0x01D0, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x0444, 0x01D4, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_CMD__NAND_ALE = IOMUX_PAD(0x0444, 0x01D4, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_CMD__ECSPI4_MOSI = IOMUX_PAD(0x0444, 0x01D4, 2, 0x055C, 2, 0), + MX7D_PAD_SD3_CMD__SAI3_RX_BCLK = IOMUX_PAD(0x0444, 0x01D4, 3, 0x06C4, 2, 0), + MX7D_PAD_SD3_CMD__GPT3_CAPTURE1 = IOMUX_PAD(0x0444, 0x01D4, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_CMD__GPIO6_IO1 = IOMUX_PAD(0x0444, 0x01D4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA0__SD3_DATA0 = IOMUX_PAD(0x0448, 0x01D8, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA0__NAND_DATA00 = IOMUX_PAD(0x0448, 0x01D8, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA0__ECSPI4_SS0 = IOMUX_PAD(0x0448, 0x01D8, 2, 0x0560, 2, 0), + MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 = IOMUX_PAD(0x0448, 0x01D8, 3, 0x06C8, 2, 0), + MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2 = IOMUX_PAD(0x0448, 0x01D8, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA0__GPIO6_IO2 = IOMUX_PAD(0x0448, 0x01D8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA1__SD3_DATA1 = IOMUX_PAD(0x044C, 0x01DC, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA1__NAND_DATA01 = IOMUX_PAD(0x044C, 0x01DC, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA1__ECSPI4_SCLK = IOMUX_PAD(0x044C, 0x01DC, 2, 0x0554, 2, 0), + MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK = IOMUX_PAD(0x044C, 0x01DC, 3, 0x06D0, 2, 0), + MX7D_PAD_SD3_DATA1__GPT3_COMPARE1 = IOMUX_PAD(0x044C, 0x01DC, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA1__GPIO6_IO3 = IOMUX_PAD(0x044C, 0x01DC, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA2__SD3_DATA2 = IOMUX_PAD(0x0450, 0x01E0, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA2__NAND_DATA02 = IOMUX_PAD(0x0450, 0x01E0, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA2__I2C3_SDA = IOMUX_PAD(0x0450, 0x01E0, IOMUX_CONFIG_SION | 2, 0x05E8, 3, 0), + MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC = IOMUX_PAD(0x0450, 0x01E0, 3, 0x06D4, 2, 0), + MX7D_PAD_SD3_DATA2__GPT3_COMPARE2 = IOMUX_PAD(0x0450, 0x01E0, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA2__GPIO6_IO4 = IOMUX_PAD(0x0450, 0x01E0, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA3__SD3_DATA3 = IOMUX_PAD(0x0454, 0x01E4, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA3__NAND_DATA03 = IOMUX_PAD(0x0454, 0x01E4, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA3__I2C3_SCL = IOMUX_PAD(0x0454, 0x01E4, IOMUX_CONFIG_SION | 2, 0x05E4, 3, 0), + MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0 = IOMUX_PAD(0x0454, 0x01E4, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA3__GPT3_COMPARE3 = IOMUX_PAD(0x0454, 0x01E4, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA3__GPIO6_IO5 = IOMUX_PAD(0x0454, 0x01E4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA4__SD3_DATA4 = IOMUX_PAD(0x0458, 0x01E8, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA4__NAND_DATA04 = IOMUX_PAD(0x0458, 0x01E8, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA4__UART3_DCE_RX = IOMUX_PAD(0x0458, 0x01E8, 3, 0x0704, 4, 0), + MX7D_PAD_SD3_DATA4__UART3_DTE_TX = IOMUX_PAD(0x0458, 0x01E8, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA4__FLEXCAN2_RX = IOMUX_PAD(0x0458, 0x01E8, 4, 0x04E0, 2, 0), + MX7D_PAD_SD3_DATA4__GPIO6_IO6 = IOMUX_PAD(0x0458, 0x01E8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA5__SD3_DATA5 = IOMUX_PAD(0x045C, 0x01EC, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA5__NAND_DATA05 = IOMUX_PAD(0x045C, 0x01EC, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA5__UART3_DCE_TX = IOMUX_PAD(0x045C, 0x01EC, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA5__UART3_DTE_RX = IOMUX_PAD(0x045C, 0x01EC, 3, 0x0704, 5, 0), + MX7D_PAD_SD3_DATA5__FLEXCAN1_TX = IOMUX_PAD(0x045C, 0x01EC, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA5__GPIO6_IO7 = IOMUX_PAD(0x045C, 0x01EC, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA6__SD3_DATA6 = IOMUX_PAD(0x0460, 0x01F0, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA6__NAND_DATA06 = IOMUX_PAD(0x0460, 0x01F0, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA6__SD3_WP = IOMUX_PAD(0x0460, 0x01F0, 2, 0x073C, 2, 0), + MX7D_PAD_SD3_DATA6__UART3_DCE_RTS = IOMUX_PAD(0x0460, 0x01F0, 3, 0x0700, 4, 0), + MX7D_PAD_SD3_DATA6__UART3_DTE_CTS = IOMUX_PAD(0x0460, 0x01F0, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA6__FLEXCAN2_TX = IOMUX_PAD(0x0460, 0x01F0, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA6__GPIO6_IO8 = IOMUX_PAD(0x0460, 0x01F0, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA7__SD3_DATA7 = IOMUX_PAD(0x0464, 0x01F4, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA7__NAND_DATA07 = IOMUX_PAD(0x0464, 0x01F4, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA7__SD3_CD_B = IOMUX_PAD(0x0464, 0x01F4, 2, 0x0738, 2, 0), + MX7D_PAD_SD3_DATA7__UART3_DCE_CTS = IOMUX_PAD(0x0464, 0x01F4, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA7__UART3_DTE_RTS = IOMUX_PAD(0x0464, 0x01F4, 3, 0x0700, 5, 0), + MX7D_PAD_SD3_DATA7__FLEXCAN1_RX = IOMUX_PAD(0x0464, 0x01F4, 4, 0x04DC, 2, 0), + MX7D_PAD_SD3_DATA7__GPIO6_IO9 = IOMUX_PAD(0x0464, 0x01F4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_STROBE__SD3_STROBE = IOMUX_PAD(0x0468, 0x01F8, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_STROBE__NAND_RE_B = IOMUX_PAD(0x0468, 0x01F8, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_STROBE__GPIO6_IO10 = IOMUX_PAD(0x0468, 0x01F8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_RESET_B__SD3_RESET_B = IOMUX_PAD(0x046C, 0x01FC, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_RESET_B__NAND_WE_B = IOMUX_PAD(0x046C, 0x01FC, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_RESET_B__SD3_RESET = IOMUX_PAD(0x046C, 0x01FC, 2, 0x0000, 0, 0), + MX7D_PAD_SD3_RESET_B__SAI3_MCLK = IOMUX_PAD(0x046C, 0x01FC, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 = IOMUX_PAD(0x046C, 0x01FC, 5, 0x0000, 0, 0), + + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 = IOMUX_PAD(0x0470, 0x0200, 0, 0x06A0, 0, 0), + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B = IOMUX_PAD(0x0470, 0x0200, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX = IOMUX_PAD(0x0470, 0x0200, 2, 0x0714, 2, 0), + MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX = IOMUX_PAD(0x0470, 0x0200, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX = IOMUX_PAD(0x0470, 0x0200, 3, 0x04DC, 3, 0), + MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD = IOMUX_PAD(0x0470, 0x0200, 4, 0x06E4, 1, 0), + MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 = IOMUX_PAD(0x0470, 0x0200, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET = IOMUX_PAD(0x0470, 0x0200, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK = IOMUX_PAD(0x0474, 0x0204, 0, 0x06A8, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B = IOMUX_PAD(0x0474, 0x0204, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX = IOMUX_PAD(0x0474, 0x0204, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX = IOMUX_PAD(0x0474, 0x0204, 2, 0x0714, 3, 0), + MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX = IOMUX_PAD(0x0474, 0x0204, 3, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK = IOMUX_PAD(0x0474, 0x0204, 4, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 = IOMUX_PAD(0x0474, 0x0204, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET = IOMUX_PAD(0x0474, 0x0204, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC = IOMUX_PAD(0x0478, 0x0208, 0, 0x06AC, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__NAND_DQS = IOMUX_PAD(0x0478, 0x0208, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS = IOMUX_PAD(0x0478, 0x0208, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS = IOMUX_PAD(0x0478, 0x0208, 2, 0x0710, 2, 0), + MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX = IOMUX_PAD(0x0478, 0x0208, 3, 0x04E0, 3, 0), + MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B = IOMUX_PAD(0x0478, 0x0208, 4, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 = IOMUX_PAD(0x0478, 0x0208, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT = IOMUX_PAD(0x0478, 0x0208, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 = IOMUX_PAD(0x047C, 0x020C, 0, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B = IOMUX_PAD(0x047C, 0x020C, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS = IOMUX_PAD(0x047C, 0x020C, 2, 0x0710, 3, 0), + MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS = IOMUX_PAD(0x047C, 0x020C, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX = IOMUX_PAD(0x047C, 0x020C, 3, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN = IOMUX_PAD(0x047C, 0x020C, 4, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 = IOMUX_PAD(0x047C, 0x020C, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET = IOMUX_PAD(0x047C, 0x020C, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC = IOMUX_PAD(0x0480, 0x0210, 0, 0x06A4, 0, 0), + MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B = IOMUX_PAD(0x0480, 0x0210, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC = IOMUX_PAD(0x0480, 0x0210, 2, 0x06B8, 1, 0), + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL = IOMUX_PAD(0x0480, 0x0210, IOMUX_CONFIG_SION | 3, 0x05EC, 3, 0), + MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD = IOMUX_PAD(0x0480, 0x0210, 4, 0x06E0, 1, 0), + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 = IOMUX_PAD(0x0480, 0x0210, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT = IOMUX_PAD(0x0480, 0x0210, 6, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0 = IOMUX_PAD(0x0480, 0x0210, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK = IOMUX_PAD(0x0484, 0x0214, 0, 0x069C, 0, 0), + MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B = IOMUX_PAD(0x0484, 0x0214, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK = IOMUX_PAD(0x0484, 0x0214, 2, 0x06B0, 1, 0), + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA = IOMUX_PAD(0x0484, 0x0214, IOMUX_CONFIG_SION | 3, 0x05F0, 3, 0), + MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA = IOMUX_PAD(0x0484, 0x0214, 4, 0x05CC, 1, 0), + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 = IOMUX_PAD(0x0484, 0x0214, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT = IOMUX_PAD(0x0484, 0x0214, 6, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1 = IOMUX_PAD(0x0484, 0x0214, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_MCLK__SAI1_MCLK = IOMUX_PAD(0x0488, 0x0218, 0, 0x0000, 0, 0), + MX7D_PAD_SAI1_MCLK__NAND_WP_B = IOMUX_PAD(0x0488, 0x0218, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_MCLK__SAI2_MCLK = IOMUX_PAD(0x0488, 0x0218, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY = IOMUX_PAD(0x0488, 0x0218, 3, 0x04F4, 3, 0), + MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB = IOMUX_PAD(0x0488, 0x0218, 4, 0x05D0, 1, 0), + MX7D_PAD_SAI1_MCLK__GPIO6_IO18 = IOMUX_PAD(0x0488, 0x0218, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK = IOMUX_PAD(0x0488, 0x0218, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC = IOMUX_PAD(0x048C, 0x021C, 0, 0x06C0, 1, 0), + MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x021C, 1, 0x0548, 1, 0), + MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX = IOMUX_PAD(0x048C, 0x021C, 2, 0x070C, 4, 0), + MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX = IOMUX_PAD(0x048C, 0x021C, 2, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS = IOMUX_PAD(0x048C, 0x021C, 3, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS = IOMUX_PAD(0x048C, 0x021C, 3, 0x06F0, 0, 0), + MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4 = IOMUX_PAD(0x048C, 0x021C, 4, 0x05BC, 1, 0), + MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 = IOMUX_PAD(0x048C, 0x021C, 5, 0x0000, 0, 0), + + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK = IOMUX_PAD(0x0490, 0x0220, 0, 0x06BC, 1, 0), + MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI = IOMUX_PAD(0x0490, 0x0220, 1, 0x054C, 1, 0), + MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX = IOMUX_PAD(0x0490, 0x0220, 2, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX = IOMUX_PAD(0x0490, 0x0220, 2, 0x070C, 5, 0), + MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS = IOMUX_PAD(0x0490, 0x0220, 3, 0x06F0, 1, 0), + MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS = IOMUX_PAD(0x0490, 0x0220, 3, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5 = IOMUX_PAD(0x0490, 0x0220, 4, 0x05C0, 1, 0), + MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 = IOMUX_PAD(0x0490, 0x0220, 5, 0x0000, 0, 0), + + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 = IOMUX_PAD(0x0494, 0x0224, 0, 0x06B4, 1, 0), + MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK = IOMUX_PAD(0x0494, 0x0224, 1, 0x0544, 1, 0), + MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS = IOMUX_PAD(0x0494, 0x0224, 2, 0x0000, 0, 0), + MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS = IOMUX_PAD(0x0494, 0x0224, 2, 0x0708, 4, 0), + MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS = IOMUX_PAD(0x0494, 0x0224, 3, 0x0000, 0, 0), + MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS = IOMUX_PAD(0x0494, 0x0224, 3, 0x06F8, 2, 0), + MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6 = IOMUX_PAD(0x0494, 0x0224, 4, 0x05C4, 1, 0), + MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 = IOMUX_PAD(0x0494, 0x0224, 5, 0x0000, 0, 0), + MX7D_PAD_SAI2_RX_DATA__KPP_COL7 = IOMUX_PAD(0x0494, 0x0224, 6, 0x0610, 1, 0), + + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 = IOMUX_PAD(0x0498, 0x0228, 0, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 = IOMUX_PAD(0x0498, 0x0228, 1, 0x0550, 1, 0), + MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS = IOMUX_PAD(0x0498, 0x0228, 2, 0x0708, 5, 0), + MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS = IOMUX_PAD(0x0498, 0x0228, 2, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS = IOMUX_PAD(0x0498, 0x0228, 3, 0x06F8, 3, 0), + MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS = IOMUX_PAD(0x0498, 0x0228, 3, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7 = IOMUX_PAD(0x0498, 0x0228, 4, 0x05C8, 1, 0), + MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 = IOMUX_PAD(0x0498, 0x0228, 5, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_DATA__KPP_ROW7 = IOMUX_PAD(0x0498, 0x0228, 6, 0x0630, 1, 0), + + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 = IOMUX_PAD(0x049C, 0x022C, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT = IOMUX_PAD(0x049C, 0x022C, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL = IOMUX_PAD(0x049C, 0x022C, IOMUX_CONFIG_SION | 2, 0x05E4, 4, 0), + MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS = IOMUX_PAD(0x049C, 0x022C, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS = IOMUX_PAD(0x049C, 0x022C, 3, 0x06F0, 2, 0), + MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0 = IOMUX_PAD(0x049C, 0x022C, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 = IOMUX_PAD(0x049C, 0x022C, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3 = IOMUX_PAD(0x049C, 0x022C, 6, 0x0620, 1, 0), + + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 = IOMUX_PAD(0x04A0, 0x0230, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT = IOMUX_PAD(0x04A0, 0x0230, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA = IOMUX_PAD(0x04A0, 0x0230, IOMUX_CONFIG_SION | 2, 0x05E8, 4, 0), + MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS = IOMUX_PAD(0x04A0, 0x0230, 3, 0x06F0, 3, 0), + MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS = IOMUX_PAD(0x04A0, 0x0230, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1 = IOMUX_PAD(0x04A0, 0x0230, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 = IOMUX_PAD(0x04A0, 0x0230, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3 = IOMUX_PAD(0x04A0, 0x0230, 6, 0x0600, 1, 0), + + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 = IOMUX_PAD(0x04A4, 0x0234, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX = IOMUX_PAD(0x04A4, 0x0234, 1, 0x04DC, 4, 0), + MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK = IOMUX_PAD(0x04A4, 0x0234, 2, 0x0534, 1, 0), + MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX = IOMUX_PAD(0x04A4, 0x0234, 3, 0x06F4, 2, 0), + MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX = IOMUX_PAD(0x04A4, 0x0234, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4 = IOMUX_PAD(0x04A4, 0x0234, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 = IOMUX_PAD(0x04A4, 0x0234, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2 = IOMUX_PAD(0x04A4, 0x0234, 6, 0x061C, 1, 0), + + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 = IOMUX_PAD(0x04A8, 0x0238, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX = IOMUX_PAD(0x04A8, 0x0238, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI = IOMUX_PAD(0x04A8, 0x0238, 2, 0x053C, 1, 0), + MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX = IOMUX_PAD(0x04A8, 0x0238, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX = IOMUX_PAD(0x04A8, 0x0238, 3, 0x06F4, 3, 0), + MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5 = IOMUX_PAD(0x04A8, 0x0238, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 = IOMUX_PAD(0x04A8, 0x0238, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2 = IOMUX_PAD(0x04A8, 0x0238, 6, 0x05FC, 1, 0), + + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x04AC, 0x023C, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 = IOMUX_PAD(0x04AC, 0x023C, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6 = IOMUX_PAD(0x04AC, 0x023C, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 = IOMUX_PAD(0x04AC, 0x023C, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1 = IOMUX_PAD(0x04AC, 0x023C, 6, 0x0618, 1, 0), + + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC = IOMUX_PAD(0x04B0, 0x0240, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER = IOMUX_PAD(0x04B0, 0x0240, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 = IOMUX_PAD(0x04B0, 0x0240, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7 = IOMUX_PAD(0x04B0, 0x0240, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 = IOMUX_PAD(0x04B0, 0x0240, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1 = IOMUX_PAD(0x04B0, 0x0240, 6, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x04B4, 0x0244, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT = IOMUX_PAD(0x04B4, 0x0244, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 = IOMUX_PAD(0x04B4, 0x0244, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8 = IOMUX_PAD(0x04B4, 0x0244, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 = IOMUX_PAD(0x04B4, 0x0244, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0 = IOMUX_PAD(0x04B4, 0x0244, 6, 0x0614, 1, 0), + + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x04B8, 0x0248, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT = IOMUX_PAD(0x04B8, 0x0248, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY = IOMUX_PAD(0x04B8, 0x0248, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9 = IOMUX_PAD(0x04B8, 0x0248, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 = IOMUX_PAD(0x04B8, 0x0248, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0 = IOMUX_PAD(0x04B8, 0x0248, 6, 0x05F4, 1, 0), + + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x04BC, 0x024C, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX = IOMUX_PAD(0x04BC, 0x024C, 1, 0x04E0, 4, 0), + MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO = IOMUX_PAD(0x04BC, 0x024C, 2, 0x0538, 1, 0), + MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL = IOMUX_PAD(0x04BC, 0x024C, IOMUX_CONFIG_SION | 3, 0x05EC, 4, 0), + MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED = IOMUX_PAD(0x04BC, 0x024C, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 = IOMUX_PAD(0x04BC, 0x024C, 5, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x04C0, 0x0250, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX = IOMUX_PAD(0x04C0, 0x0250, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 = IOMUX_PAD(0x04C0, 0x0250, 2, 0x0540, 1, 0), + MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA = IOMUX_PAD(0x04C0, 0x0250, IOMUX_CONFIG_SION | 3, 0x05F0, 4, 0), + MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ = IOMUX_PAD(0x04C0, 0x0250, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 = IOMUX_PAD(0x04C0, 0x0250, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x04C0, 0x0250, 7, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x04C4, 0x0254, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC = IOMUX_PAD(0x04C4, 0x0254, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 = IOMUX_PAD(0x04C4, 0x0254, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 = IOMUX_PAD(0x04C4, 0x0254, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 = IOMUX_PAD(0x04C4, 0x0254, 5, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC = IOMUX_PAD(0x04C8, 0x0258, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER = IOMUX_PAD(0x04C8, 0x0258, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK = IOMUX_PAD(0x04C8, 0x0258, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 = IOMUX_PAD(0x04C8, 0x0258, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 = IOMUX_PAD(0x04C8, 0x0258, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 = IOMUX_PAD(0x04C8, 0x0258, 5, 0x0000, 0, 0), + + MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x04CC, 0x025C, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x04CC, 0x025C, 1, 0x0564, 2, 0), + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 = IOMUX_PAD(0x04CC, 0x025C, 2, 0x06A0, 1, 0), + MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3 = IOMUX_PAD(0x04CC, 0x025C, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ = IOMUX_PAD(0x04CC, 0x025C, 4, 0x057C, 1, 0), + MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 = IOMUX_PAD(0x04CC, 0x025C, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 = IOMUX_PAD(0x04CC, 0x025C, 6, 0x04E4, 2, 0), + MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0 = IOMUX_PAD(0x04CC, 0x025C, 7, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK = IOMUX_PAD(0x04D0, 0x0260, 0, 0x056C, 0, 0), + MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B = IOMUX_PAD(0x04D0, 0x0260, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK = IOMUX_PAD(0x04D0, 0x0260, 2, 0x06A8, 1, 0), + MX7D_PAD_ENET1_RX_CLK__GPT2_CLK = IOMUX_PAD(0x04D0, 0x0260, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE = IOMUX_PAD(0x04D0, 0x0260, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 = IOMUX_PAD(0x04D0, 0x0260, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 = IOMUX_PAD(0x04D0, 0x0260, 6, 0x04E8, 2, 0), + MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1 = IOMUX_PAD(0x04D0, 0x0260, 7, 0x0000, 0, 0), + + MX7D_PAD_ENET1_CRS__ENET1_CRS = IOMUX_PAD(0x04D4, 0x0264, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x04D4, 0x0264, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC = IOMUX_PAD(0x04D4, 0x0264, 2, 0x06AC, 1, 0), + MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1 = IOMUX_PAD(0x04D4, 0x0264, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0 = IOMUX_PAD(0x04D4, 0x0264, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__GPIO7_IO14 = IOMUX_PAD(0x04D4, 0x0264, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 = IOMUX_PAD(0x04D4, 0x0264, 6, 0x04EC, 2, 0), + MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2 = IOMUX_PAD(0x04D4, 0x0264, 7, 0x0000, 0, 0), + + MX7D_PAD_ENET1_COL__ENET1_COL = IOMUX_PAD(0x04D8, 0x0268, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY = IOMUX_PAD(0x04D8, 0x0268, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 = IOMUX_PAD(0x04D8, 0x0268, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__GPT2_CAPTURE2 = IOMUX_PAD(0x04D8, 0x0268, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1 = IOMUX_PAD(0x04D8, 0x0268, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__GPIO7_IO15 = IOMUX_PAD(0x04D8, 0x0268, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 = IOMUX_PAD(0x04D8, 0x0268, 6, 0x04F0, 2, 0), + MX7D_PAD_ENET1_COL__CSU_INT_DEB = IOMUX_PAD(0x04D8, 0x0268, 7, 0x0000, 0, 0), +}; +#endif /* __ASM_ARCH_IMX7D_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx7/sys_proto.h b/arch/arm/include/asm/arch-mx7/sys_proto.h new file mode 100644 index 0000000..e6a1a88 --- /dev/null +++ b/arch/arm/include/asm/arch-mx7/sys_proto.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +#include <asm/imx-common/regs-common.h> +#include "../arch-imx/cpu.h" + +#define is_soc_rev(rev) ((int)((get_cpu_rev() & 0xFF) - rev)) +u32 get_cpu_rev(void); + +/* returns MXC_CPU_ value */ +#define cpu_type(rev) (((rev) >> 12)&0xff) + +/* use with MXC_CPU_ constants */ +#define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu) + +const char *get_imx_type(u32 imxtype); +unsigned imx_ddr_size(void); +void set_wdog_reset(struct wdog_regs *wdog); + +int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data); +int arch_auxiliary_core_check_up(u32 core_id); + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ + +int fecmxc_initialize(bd_t *bis); +u32 get_ahb_clk(void); +u32 get_periph_clk(void); + +int mxs_reset_block(struct mxs_register_32 *reg); +int mxs_wait_mask_set(struct mxs_register_32 *reg, + uint32_t mask, + unsigned int timeout); +int mxs_wait_mask_clr(struct mxs_register_32 *reg, + uint32_t mask, + unsigned int timeout); +#endif diff --git a/arch/arm/include/asm/imx-common/boot_mode.h b/arch/arm/include/asm/imx-common/boot_mode.h index de0205c..62dd01d 100644 --- a/arch/arm/include/asm/imx-common/boot_mode.h +++ b/arch/arm/include/asm/imx-common/boot_mode.h @@ -9,6 +9,27 @@ #define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \ ((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1)

+enum boot_device { + WEIM_NOR_BOOT, + ONE_NAND_BOOT, + PATA_BOOT, + SATA_BOOT, + I2C_BOOT, + SPI_NOR_BOOT, + SD1_BOOT, + SD2_BOOT, + SD3_BOOT, + SD4_BOOT, + MMC1_BOOT, + MMC2_BOOT, + MMC3_BOOT, + MMC4_BOOT, + NAND_BOOT, + QSPI_BOOT, + UNKNOWN_BOOT, + BOOT_DEV_NUM = UNKNOWN_BOOT, +}; + struct boot_mode { const char *name; unsigned cfg_val; diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 482a4bd..9e9cb55 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -7,7 +7,7 @@

obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o -ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610 ls102xa)) +ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610 ls102xa)) obj-y += imx_watchdog.o endif obj-$(CONFIG_S5P) += s5p_wdt.o