Use Kconfig option to select chassis version.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/powerpc/cpu/mpc85xx/Kconfig | 21 +++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 10 ---------- scripts/config_whitelist.txt | 2 -- 3 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 8b905e2..ac6c197 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -341,6 +341,7 @@ config ARCH_B4420 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -362,6 +363,7 @@ config ARCH_B4860 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -641,6 +643,7 @@ config ARCH_P2041 select SYS_FSL_ERRATUM_USB14 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -663,6 +666,7 @@ config ARCH_P3041 select SYS_FSL_ERRATUM_USB14 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -696,6 +700,7 @@ config ARCH_P4080 select SYS_P4080_ERRATUM_SERDES_A005 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -714,6 +719,7 @@ config ARCH_P5020 select SYS_FSL_ERRATUM_USB14 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -732,6 +738,7 @@ config ARCH_P5040 select SYS_FSL_ERRATUM_USB14 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -750,6 +757,7 @@ config ARCH_T1023 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5
@@ -765,6 +773,7 @@ config ARCH_T1024 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5
@@ -781,6 +790,7 @@ config ARCH_T1040 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5
@@ -797,6 +807,7 @@ config ARCH_T1042 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5
@@ -814,6 +825,7 @@ config ARCH_T2080 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -831,6 +843,7 @@ config ARCH_T2081 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -849,6 +862,7 @@ config ARCH_T4160 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -868,6 +882,7 @@ config ARCH_T4240 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4
@@ -1127,6 +1142,12 @@ config SYS_P4080_ERRATUM_SERDES_A001 config SYS_P4080_ERRATUM_SERDES_A005 bool
+config SYS_FSL_QORIQ_CHASSIS1 + bool + +config SYS_FSL_QORIQ_CHASSIS2 + bool + config SYS_FSL_NUM_LAWS int "Number of local access windows" depends on FSL_LAW diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 92c96d7..8cde05c 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -117,7 +117,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ -#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_NUM_FMAN 1 @@ -136,7 +135,6 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P3041) -#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_NUM_FMAN 1 @@ -155,7 +153,6 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ -#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_NUM_FMAN 2 @@ -176,7 +173,6 @@
#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */ #define CONFIG_SYS_PPC64 /* 64-bit core */ -#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_NUM_FMAN 1 @@ -196,7 +192,6 @@
#elif defined(CONFIG_ARCH_P5040) #define CONFIG_SYS_PPC64 -#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_NUM_FMAN 2 @@ -240,7 +235,6 @@ #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #ifdef CONFIG_ARCH_T4240 @@ -285,7 +279,6 @@ #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ @@ -334,7 +327,6 @@ #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) #define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 @@ -367,7 +359,6 @@ #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) #define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_SYS_FMAN_V3 @@ -399,7 +390,6 @@ #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_QMAN_V3 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 2cc8f0c..241d047 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -5461,8 +5461,6 @@ CONFIG_SYS_FSL_QBMAN_SIZE_1 CONFIG_SYS_FSL_QMAN_ADDR CONFIG_SYS_FSL_QMAN_OFFSET CONFIG_SYS_FSL_QMAN_V3 -CONFIG_SYS_FSL_QORIQ_CHASSIS1 -CONFIG_SYS_FSL_QORIQ_CHASSIS2 CONFIG_SYS_FSL_QSPI_AHB CONFIG_SYS_FSL_QSPI_BASE CONFIG_SYS_FSL_QSPI_BASE1