Hi Giulio,
This commit adds board support for i.MXRT1050-EVK from NXP. This board is an evaluation kit provided by NXP for i.MXRT105x processor family.
More information about this board can be found here: https://www.nxp.com/design/development-boards/i.mx-evaluation-and-developmen...
The initial supported/tested devices include:
- Debug serial
- SD
Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com
V1->V2:
- introduced CONFIG_IMXRT1050
- added imxrt1050-evk-u-boot.dtsi for imxrt1050-evk.dts
arch/arm/dts/Makefile | 2 + arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 44 ++++ arch/arm/dts/imxrt1050-evk.dts | 200 ++++++++++++++++++ arch/arm/mach-imx/imxrt/Kconfig | 12 ++ board/freescale/imxrt1050-evk/Kconfig | 22 ++ board/freescale/imxrt1050-evk/MAINTAINERS | 6 + board/freescale/imxrt1050-evk/Makefile | 6 + board/freescale/imxrt1050-evk/README | 31 +++ board/freescale/imxrt1050-evk/imximage.cfg | 36 ++++ board/freescale/imxrt1050-evk/imxrt1050-evk.c | 81 +++++++ configs/imxrt1050-evk_defconfig | 69 ++++++ include/configs/imxrt1050-evk.h | 46 ++++ 12 files changed, 555 insertions(+) create mode 100644 arch/arm/dts/imxrt1050-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imxrt1050-evk.dts create mode 100644 board/freescale/imxrt1050-evk/Kconfig create mode 100644 board/freescale/imxrt1050-evk/MAINTAINERS create mode 100644 board/freescale/imxrt1050-evk/Makefile create mode 100644 board/freescale/imxrt1050-evk/README create mode 100644 board/freescale/imxrt1050-evk/imximage.cfg create mode 100644 board/freescale/imxrt1050-evk/imxrt1050-evk.c create mode 100644 configs/imxrt1050-evk_defconfig create mode 100644 include/configs/imxrt1050-evk.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 983e235f44..0864460751 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -707,6 +707,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-evk.dtb \ imx8mp-evk.dtb
+dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb
dtb-$(CONFIG_RCAR_GEN2) += \ r8a7790-lager-u-boot.dtb \ r8a7790-stout-u-boot.dtb \ diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi new file mode 100644 index 0000000000..fb4f7f6f9d --- /dev/null +++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi
Ach... Ok, so you have already used the U-Boot specific dtsi.
@@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/*
- Copyright (C) 2019
- Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
- */
+/ {
- chosen {
u-boot,dm-spl;- };
+};
+&lpuart1 { /* console */
- u-boot,dm-spl;
+};
+&semc {
- bank1: bank@0 {
u-boot,dm-spl;- };
+};
+&iomuxc {
- u-boot,dm-spl;
- imxrt1050-evk {
u-boot,dm-spl;pinctrl_lpuart1: lpuart1grp {u-boot,dm-spl;};pinctrl_semc: semcgrp {u-boot,dm-spl;};pinctrl_usdhc0: usdhc0grp {u-boot,dm-spl;};- };
+};
+&usdhc1 {
- u-boot,dm-spl;
+}; diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts new file mode 100644 index 0000000000..56b75986e2 --- /dev/null +++ b/arch/arm/dts/imxrt1050-evk.dts @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/*
- Copyright (C) 2019
- Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
- */
+/dts-v1/; +#include "imxrt1050.dtsi" +#include "imxrt1050-evk-u-boot.dtsi" +#include <dt-bindings/pinctrl/pins-imxrt1050.h>
+/ {
- model = "NXP IMXRT1050-evk board";
- compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
- chosen {
bootargs = "root=/dev/ram";stdout-path = "serial0:115200n8";- };
- memory {
reg = <0x80000000 0x2000000>;- };
+};
+&lpuart1 { /* console */
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpuart1>;
- status = "okay";
+};
+&semc {
- /*
* Memory configuration from sdram datasheet IS42S16160J-6BLI*/- fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
MUX_CSX0_SDRAM_CS10000>;- fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
BL_8COL_9BITSCL_3>;- fsl,sdram-timing = /bits/ 8 <0x2
0x20x90x10x50x60x200x090x010x000x040x0A0x210x50>;- bank1: bank@0 {
fsl,base-address = <0x80000000>;fsl,memory-size = <MEM_SIZE_32M>;- };
+};
+&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpuart1>;
- imxrt1050-evk {
pinctrl_lpuart1: lpuart1grp {fsl,pins = <MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
0xf1MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
0xf1>;};pinctrl_semc: semcgrp {fsl,pins = <MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA000xf1 /* SEMC_D0 */MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA010xf1 /* SEMC_D1 */MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA020xf1 /* SEMC_D2 */MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA030xf1 /* SEMC_D3 */MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA040xf1 /* SEMC_D4 */MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA050xf1 /* SEMC_D5 */MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA060xf1 /* SEMC_D6 */MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA070xf1 /* SEMC_D7 */MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM000xf1 /* SEMC_DM0 */MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
0xf1 /* SEMC_A0 */MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
0xf1 /* SEMC_A1 */MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
0xf1 /* SEMC_A2 */MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
0xf1 /* SEMC_A3 */MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
0xf1 /* SEMC_A4 */MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
0xf1 /* SEMC_A5 */MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
0xf1 /* SEMC_A6 */MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
0xf1 /* SEMC_A7 */MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
0xf1 /* SEMC_A8 */MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
0xf1 /* SEMC_A9 */MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
0xf1 /* SEMC_A11 */MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
0xf1 /* SEMC_A12 */MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA00xf1 /* SEMC_BA0 */MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA10xf1 /* SEMC_BA1 */MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
0xf1 /* SEMC_A10 */MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS0xf1 /* SEMC_CAS */MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS0xf1 /* SEMC_RAS */MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK0xf1 /* SEMC_CLK */MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE0xf1 /* SEMC_CKE */MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE0xf1 /* SEMC_WE */MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS00xf1 /* SEMC_CS0 */MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA080xf1 /* SEMC_D8 */MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA090xf1 /* SEMC_D9 */MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA100xf1 /* SEMC_D10 */MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA110xf1 /* SEMC_D11 */MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA120xf1 /* SEMC_D12 */MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA130xf1 /* SEMC_D13 */MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA140xf1 /* SEMC_D14 */MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA150xf1 /* SEMC_D15 */MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM010xf1 /* SEMC_DM1 */MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS(IMX_PAD_SION | 0xf1)/* SEMC_DQS */
>;};pinctrl_usdhc0: usdhc0grp {fsl,pins = <MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
0x1B000MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
0xB069MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD
0x17061MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK
0x17061MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
0x17061MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
0x17061MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
0x17061MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
0x17061>;};- };
+};
+&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz",
"sleep";
- pinctrl-0 = <&pinctrl_usdhc0>;
- pinctrl-1 = <&pinctrl_usdhc0>;
- pinctrl-2 = <&pinctrl_usdhc0>;
- pinctrl-3 = <&pinctrl_usdhc0>;
- status = "okay";
- cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+}; diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig index 96ad2e988b..e3aff11d48 100644 --- a/arch/arm/mach-imx/imxrt/Kconfig +++ b/arch/arm/mach-imx/imxrt/Kconfig @@ -10,4 +10,16 @@ config IMXRT1050 config SYS_SOC default "imxrt"
+choice
- prompt "NXP i.MXRT board select"
- optional
+config TARGET_IMXRT1050_EVK
- bool "Support imxrt1050 EVK board"
- select IMXRT1050
+endchoice
+source "board/freescale/imxrt1050-evk/Kconfig"
endif diff --git a/board/freescale/imxrt1050-evk/Kconfig b/board/freescale/imxrt1050-evk/Kconfig new file mode 100644 index 0000000000..79e6e4524a --- /dev/null +++ b/board/freescale/imxrt1050-evk/Kconfig @@ -0,0 +1,22 @@ +if TARGET_IMXRT1050_EVK
+config SYS_BOARD
- string
- default "imxrt1050-evk"
+config SYS_VENDOR
- string
- default "freescale"
+config SYS_SOC
- string
- default "imxrt1050"
+config SYS_CONFIG_NAME
- string
- default "imxrt1050-evk"
+config IMX_CONFIG
- default "board/freescale/imxrt1050-evk/imximage.cfg"
+endif diff --git a/board/freescale/imxrt1050-evk/MAINTAINERS b/board/freescale/imxrt1050-evk/MAINTAINERS new file mode 100644 index 0000000000..a872855452 --- /dev/null +++ b/board/freescale/imxrt1050-evk/MAINTAINERS @@ -0,0 +1,6 @@ +IMXRT1050 EVALUATION KIT +M: Giulio Benetti giulio.benetti@benettiengineering.com +S: Maintained +F: board/freescale/imxrt1050-evk +F: include/configs/imxrt1050-evk.h +F: configs/imxrt1050-evk_defconfig diff --git a/board/freescale/imxrt1050-evk/Makefile b/board/freescale/imxrt1050-evk/Makefile new file mode 100644 index 0000000000..0e984d1d7a --- /dev/null +++ b/board/freescale/imxrt1050-evk/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 +# Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
+obj-y := imxrt1050-evk.o diff --git a/board/freescale/imxrt1050-evk/README b/board/freescale/imxrt1050-evk/README new file mode 100644 index 0000000000..f7e2894025 --- /dev/null +++ b/board/freescale/imxrt1050-evk/README @@ -0,0 +1,31 @@ +How to use U-Boot on NXP i.MXRT1050 EVK +-----------------------------------------------
+- Build U-Boot for i.MXRT1050 EVK:
+$ make mrproper +$ make imxrt1050-evk_defconfig +$ make
+This will generate the SPL image called SPL and the u-boot.img.
+- Flash the SPL image into the micro SD card:
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+- Flash the u-boot.img image into the micro SD card:
+sudo dd if=u-boot.img of=/dev/sdb bs=1k seek=128; sync
+- Jumper settings:
+SW7: 1 0 1 0
+where 0 means bottom position and 1 means top position (from the +switch label numbers reference).
+- Connect the USB cable between the EVK and the PC for the console. +(The USB console connector is the one close the ethernet connector)
+- Insert the micro SD card in the board, power it up and U-Boot messages should +come up.
Thanks for detailed readme, appreciated :-)
diff --git a/board/freescale/imxrt1050-evk/imximage.cfg b/board/freescale/imxrt1050-evk/imximage.cfg new file mode 100644 index 0000000000..cf1665be61 --- /dev/null +++ b/board/freescale/imxrt1050-evk/imximage.cfg @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2019
- Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
- */
+#define __ASSEMBLY__ +#include <config.h>
+/* image version */
+IMAGE_VERSION 2
+/*
- Boot Device : one of
- spi/sd/nand/onenand, qspi/nor
- */
+BOOT_FROM sd
+/*
- Device Configuration Data (DCD)
- Each entry must have the format:
- Addr-type Address Value
- where:
- Addr-type register length (1,2 or 4 bytes)
- Address absolute address of the register
- value value to be stored in the register
- */
+/* Set all FlexRAM as OCRAM(01b) */ +DATA 4 0x400AC044 0x55555555 +/* Use FLEXRAM_BANK_CFG to config FlexRAM */ +SET_BIT 4 0x400AC040 0x4 diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c b/board/freescale/imxrt1050-evk/imxrt1050-evk.c new file mode 100644 index 0000000000..bda03b5ea5 --- /dev/null +++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2019
If you would prepare next version of this patch - please update the date.
- Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
- */
+#include <common.h> +#include <dm.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/armv7m.h>
+DECLARE_GLOBAL_DATA_PTR;
+int dram_init(void) +{ +#ifndef CONFIG_SUPPORT_SPL
- int rv;
- struct udevice *dev;
- rv = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (rv) {
debug("DRAM init failed: %d\n", rv);return rv;- }
+#endif
- return fdtdec_setup_mem_size_base();
+}
+int dram_init_banksize(void) +{
- return fdtdec_setup_memory_banksize();
+}
+#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{
- debug("SPL: booting kernel\n");
- /* break into full u-boot on 'c' */
- return serial_tstc() && serial_getc() == 'c';
+} +#endif
+int spl_dram_init(void) +{
- struct udevice *dev;
- int rv;
- rv = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (rv)
debug("DRAM init failed: %d\n", rv);- return rv;
+}
+void spl_board_init(void) +{
- spl_dram_init();
- preloader_console_init();
- arch_cpu_init(); /* to configure mpu for sdram rw
permissions */ +}
+u32 spl_boot_device(void) +{
- return BOOT_DEVICE_MMC1;
+} +#endif
+u32 get_board_rev(void) +{
- return 0;
+}
+int board_init(void) +{
- gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
- return 0;
+} diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig new file mode 100644 index 0000000000..102e663886 --- /dev/null +++ b/configs/imxrt1050-evk_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_SYS_ICACHE_OFF=y +CONFIG_SYS_DCACHE_OFF=y
Isn't there any cache available on this SoC? Or is it handled differently and requires special CONFIG_ option?
Enabling caches brings significant speed improvement also in U-Boot.
+CONFIG_ARCH_IMXRT=y +CONFIG_SYS_TEXT_BASE=0x80002000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_OFFSET=0x80000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_IMXRT1050_EVK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_SIZE_LIMIT=131072 +CONFIG_SPL=y +CONFIG_SPL_TEXT_BASE=0x20209000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SD_BOOT=y +# CONFIG_USE_BOOTCOMMAND is not set +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 +# CONFIG_SPL_CRC32_SUPPORT is not set +# CONFIG_SPL_DM_GPIO is not set +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_MII is not set +# CONFIG_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk" +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_TFTP_BLOCKSIZE=512 +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +# CONFIG_OF_TRANSLATE is not set +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMXRT1050=y +CONFIG_CLK_IMXRT1050=y +CONFIG_MXC_GPIO=y +# CONFIG_INPUT is not set +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMXRT=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_IMXRT_SDRAM=y +CONFIG_FSL_LPUART=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_HEXDUMP=y diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h new file mode 100644 index 0000000000..cdec657fb0 --- /dev/null +++ b/include/configs/imxrt1050-evk.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2019
- Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
- */
+#ifndef __IMXRT1050_EVK_H +#define __IMXRT1050_EVK_H
+#include <asm/arch/imx-regs.h>
+#define CONFIG_SYS_INIT_SP_ADDR 0x20280000
+#ifdef CONFIG_SUPPORT_SPL +#define CONFIG_SYS_LOAD_ADDR 0x20209000 +#else +#define CONFIG_SYS_LOAD_ADDR 0x80000000 +#define CONFIG_LOADADDR 0x80000000 +#endif
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
+#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE (32 * 1024 * 1024)
+#define DMAMEM_SZ_ALL (1 * 1024 * 1024) +#define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \
DMAMEM_SZ_ALL)+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
+/*
- Configuration of the external SDRAM memory
- */
+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
+/* For SPL */ +#ifdef CONFIG_SUPPORT_SPL +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_SPL_LEN 0x00008000 +#define CONFIG_SYS_UBOOT_START 0x800023FD +#endif +/* For SPL ends */
+#endif /* __IMXRT1050_EVK_H */
Best regards,
Lukasz Majewski
--
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