454179: Stale prediction may inhibit target address misprediction on next predicted taken branch Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1
Also provide a hook for SoC specific handling to take place if needed.
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon nm@ti.com --- README | 1 + arch/arm/cpu/armv7/cp15.c | 6 ++++++ arch/arm/cpu/armv7/start.S | 13 +++++++++++++ arch/arm/include/asm/armv7.h | 2 ++ 4 files changed, 22 insertions(+)
diff --git a/README b/README index 9a0106066b1c..259dbdbd2075 100644 --- a/README +++ b/README @@ -693,6 +693,7 @@ The following options need to be configured: NOTE: The following can be machine specific errata. These do have ability to provide rudimentary version and machine specific checks, but expect no product checks. + CONFIG_ARM_ERRATA_454179 CONFIG_ARM_ERRATA_798870
- Driver Model diff --git a/arch/arm/cpu/armv7/cp15.c b/arch/arm/cpu/armv7/cp15.c index 8ac81c9ba147..b44c9f94a822 100644 --- a/arch/arm/cpu/armv7/cp15.c +++ b/arch/arm/cpu/armv7/cp15.c @@ -21,3 +21,9 @@ void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 cpu_midr, { asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr)); } + +void __weak v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, + u32 cpu_variant, u32 cpu_rev) +{ + asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(acr)); +} diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 89637e26395d..8483687879ed 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -189,6 +189,19 @@ ENTRY(cpu_init_cp15) skip_errata_798870: #endif
+#ifdef CONFIG_ARM_ERRATA_454179 + cmp r2, #0x21 @ Only on < r2p1 + bge skip_errata_454179 + + mrc p15, 0, r0, c1, c0, 1 @ Read ACR + orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits + push {r1-r5} @ Save the cpu info registers + bl v7_arch_cp15_set_acr + pop {r1-r5} @ Restore the cpu info - fall through + +skip_errata_454179: +#endif + mov pc, r5 @ back to my caller ENDPROC(cpu_init_cp15)
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index 69abc4791ae5..e9a00e20002c 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -141,6 +141,8 @@ extern char __secure_end[]; void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, u32 cpu_rev_comb, u32 cpu_variant, u32 cpu_rev); +void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, + u32 cpu_variant, u32 cpu_rev); #endif /* ! __ASSEMBLY__ */
#endif