From: Sekhar Nori nsekhar@ti.com
Provides initial support for TI OMAP-L1x/DA8xx SoC devices. See http://www.ti.com
Provides: Low level initialisation. System clock API. Timer control.
Signed-off-by: Nick Thompson nick.thompson@gefanuc.com --- Applies to u-boot-ti
cpu/arm926ejs/davinci/cpu.c | 43 ++++++++++++++++++++++++++++++++++++++++++- cpu/arm926ejs/davinci/psc.c | 43 ++++++++++++++++++++++++++++++++++--------- 2 files changed, 76 insertions(+), 10 deletions(-)
diff --git a/cpu/arm926ejs/davinci/cpu.c b/cpu/arm926ejs/davinci/cpu.c index 390cab8..a18f7e9 100644 --- a/cpu/arm926ejs/davinci/cpu.c +++ b/cpu/arm926ejs/davinci/cpu.c @@ -23,7 +23,7 @@ #include <common.h> #include <netdev.h> #include <asm/arch/hardware.h> - +#include <asm/io.h>
/* offsets from PLL controller base */ #define PLLC_PLLCTL 0x100 @@ -60,6 +60,47 @@ #define DDR_PLLDIV PLLC_PLLDIV1 #endif
+#ifdef CONFIG_SOC_DA8XX +const dv_reg * const sysdiv[7] = { + &DAVINCI_PLLC_REGS->plldiv1, &DAVINCI_PLLC_REGS->plldiv2, + &DAVINCI_PLLC_REGS->plldiv3, &DAVINCI_PLLC_REGS->plldiv4, + &DAVINCI_PLLC_REGS->plldiv5, &DAVINCI_PLLC_REGS->plldiv6, + &DAVINCI_PLLC_REGS->plldiv7 +}; + +int clk_get(enum davinci_clk_ids id) +{ + int pre_div = (readl(&DAVINCI_PLLC_REGS->prediv) & + DAVINCI_PPLC_DIV_MASK) + 1; + int pllm = readl(&DAVINCI_PLLC_REGS->pllm) + 1; + int post_div = (readl(&DAVINCI_PLLC_REGS->postdiv) & + DAVINCI_PPLC_DIV_MASK) + 1; + int pll_out = CONFIG_SYS_OSCIN_FREQ; + + if (id == DAVINCI_AUXCLK_CLKID) + goto out; + + /* + * Lets keep this simple. Combining operations can result in + * unexpected approximations + */ + pll_out /= pre_div; + pll_out *= pllm; + + if (id == DAVINCI_PLLM_CLKID) + goto out; + + pll_out /= post_div; + + if (id == DAVINCI_PLLC_CLKID) + goto out; + + pll_out /= (readl(sysdiv[id - 1]) & DAVINCI_PPLC_DIV_MASK) + 1; + +out: + return pll_out; +} +#endif /* CONFIG_SOC_DA8XX */
#ifdef CONFIG_DISPLAY_CPUINFO
diff --git a/cpu/arm926ejs/davinci/psc.c b/cpu/arm926ejs/davinci/psc.c index 5bb972f..33a1d1c 100644 --- a/cpu/arm926ejs/davinci/psc.c +++ b/cpu/arm926ejs/davinci/psc.c @@ -25,6 +25,7 @@
#include <common.h> #include <asm/arch/hardware.h> +#include <asm/io.h>
/* * The PSC manages three inputs to a "module" which may be a peripheral or @@ -47,21 +48,45 @@ /* Works on Always On power domain only (no PD argument) */ void lpsc_on(unsigned int id) { - dv_reg_p mdstat, mdctl; + dv_reg_p mdstat, mdctl, ptstat, ptcmd; +#ifdef CONFIG_SOC_DA8XX + struct davinci_psc_regs *psc_regs; +#endif
+#ifndef CONFIG_SOC_DA8XX if (id >= DAVINCI_LPSC_GEM) return; /* Don't work on DSP Power Domain */
mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + ptstat = REG_P(PSC_PTSTAT); + ptcmd = REG_P(PSC_PTCMD); +#else + if (id < DAVINCI_LPSC_PSC1_BASE) { + if (id >= PSC_PSC0_MODULE_ID_CNT) + return; + psc_regs = DAVINCI_PSC0_REGS; + mdstat = &psc_regs->psc0.mdstat[id]; + mdctl = &psc_regs->psc0.mdctl[id]; + } else { + id -= DAVINCI_LPSC_PSC1_BASE; + if (id >= PSC_PSC1_MODULE_ID_CNT) + return; + psc_regs = DAVINCI_PSC1_REGS; + mdstat = &psc_regs->psc1.mdstat[id]; + mdctl = &psc_regs->psc1.mdctl[id]; + } + ptstat = &psc_regs->ptstat; + ptcmd = &psc_regs->ptcmd; +#endif
- while (REG(PSC_PTSTAT) & 0x01) + while (readl(ptstat) & 0x01) continue;
- if ((*mdstat & 0x1f) == 0x03) - return; /* Already on and enabled */ + if ((readl(mdstat) & 0x1f) == 0x03) + return; /* Already on and enabled */
- *mdctl |= 0x03; + writel(readl(mdctl) | 0x03, mdctl);
switch (id) { #ifdef CONFIG_SOC_DM644X @@ -80,16 +105,16 @@ void lpsc_on(unsigned int id) case DAVINCI_LPSC_MEMSTICK: case DAVINCI_LPSC_McBSP: case DAVINCI_LPSC_GPIO: - *mdctl |= 0x200; + writel(readl(mdctl) | 0x200, mdctl); break; #endif }
- REG(PSC_PTCMD) = 0x01; + writel(0x01, ptcmd);
- while (REG(PSC_PTSTAT) & 0x03) + while (readl(ptstat) & 0x01) continue; - while ((*mdstat & 0x1f) != 0x03) /* Probably an overkill... */ + while ((readl(mdstat) & 0x1f) != 0x03) continue; }