Re: [U-Boot] [PATCH V3 3/9] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420

Dear Ajay Kumar,

On 4 July 2014 22:19, Ajay Kumar ajaykumar.rs@samsung.com wrote:

Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver. Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.

Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com Acked-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org

---

arch/arm/cpu/armv7/exynos/clock.c | 83 +++++++++++++++++++++++++++-- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +- arch/arm/include/asm/arch-exynos/clk.h | 1 + 3 files changed, 80 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 400d134..c8be39b 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) * VPLL_CON: MIDV [24:16] * BPLL_CON: MIDV [25:16]: Exynos5 */

•   if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
  

•   if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
  

•       pllreg == SPLL)
            mask = 0x3ff;
    else
            mask = 0x1ff;
  

@@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg) r = readl(&clk->rpll_con0); k = readl(&clk->rpll_con1); break;

•   case SPLL:
  

•           r = readl(&clk->spll_con0);
  

•           break;
    default:
            printf("Unsupported PLL (%d)\n", pllreg);
            return 0;
  

@@ -1027,6 +1031,40 @@ static unsigned long exynos5_get_lcd_clk(void) return pclk; }

+static unsigned long exynos5420_get_lcd_clk(void) +{

•   struct exynos5420_clock *clk =
  

•           (struct exynos5420_clock *)samsung_get_base_clock();
  

•   unsigned long pclk, sclk;
  

•   unsigned int sel;
  

•   unsigned int ratio;
  

•   /*
  

•    * CLK_SRC_DISP10
  

•    * FIMD1_SEL [4]
  

•    * 0: SCLK_RPLL
  

•    * 1: SCLK_SPLL
  

•    */
  

•   sel = readl(&clk->src_disp10);
  

•   sel &= (1 << 4);
  

•   if (sel)
  

•           sclk = get_pll_clk(SPLL);
  

•   else
  

•           sclk = get_pll_clk(RPLL);
  

•   /*
  

•    * CLK_DIV_DISP10
  

•    * FIMD1_RATIO [3:0]
  

•    */
  

•   ratio = readl(&clk->div_disp10);
  

•   ratio = ratio & 0xf;
  

•   pclk = sclk / (ratio + 1);
  

•   return pclk;
  

+}

void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1131,6 +1169,33 @@ void exynos5_set_lcd_clk(void) clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0); }

+void exynos5420_set_lcd_clk(void) +{

•   struct exynos5420_clock *clk =
  

•           (struct exynos5420_clock *)samsung_get_base_clock();
  

•   unsigned int cfg;
  

•   /*
  

•    * CLK_SRC_DISP10
  

•    * FIMD1_SEL [4]
  

•    * 0: SCLK_RPLL
  

•    * 1: SCLK_SPLL
  

•    */
  

•   cfg = readl(&clk->src_disp10);
  

•   cfg &= ~(0x1 << 4);
  

•   cfg |= (0 << 4);
  

•   writel(cfg, &clk->src_disp10);
  

•   /*
  

•    * CLK_DIV_DISP10
  

•    * FIMD1_RATIO          [3:0]
  

•    */
  

•   cfg = readl(&clk->div_disp10);
  

•   cfg &= ~(0xf << 0);
  

•   cfg |= (0 << 0);
  

•   writel(cfg, &clk->div_disp10);
  

+}

void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = @@ -1602,16 +1667,24 @@ unsigned long get_lcd_clk(void) { if (cpu_is_exynos4()) return exynos4_get_lcd_clk();

•   else
  

•           return exynos5_get_lcd_clk();
  

•   else {
  

•           if (proid_is_exynos5420())
  

•                   return exynos5420_get_lcd_clk();
  

•           else
  

•                   return exynos5_get_lcd_clk();
  

•   }
  

}

void set_lcd_clk(void) { if (cpu_is_exynos4()) exynos4_set_lcd_clk();

•   else
  

•           exynos5_set_lcd_clk();
  

•   else {
  

•           if (proid_is_exynos5250())
  

•                   exynos5_set_lcd_clk();
  

•           if (proid_is_exynos5420())
  
  

else if

•                   exynos5420_set_lcd_clk();
  

•   }
  

}

Thanks, Minkyu Kang