Hi Scott,
On Tue, 19 Mar 2013 18:32:39 -0500, Scott Wood scottwood@freescale.com wrote:
On 03/19/2013 05:07:33 PM, York Sun wrote:
On 03/19/2013 03:01 PM, Albert ARIBAUD wrote:
What's the point of this command exactly? I can see the point of
range
flushes (and invalidates) in the code for drivers that use DMA, but
as a
shell command, I fail to see the interest of it.
I am actually expecting this question. We have a situation that an application is copied by u-boot to its destination in memory. The code needs to be "seen" in the main memory. Without flushing cache, it is only visible to cores.
It's the same purpose as the cache flushing that happens in bootm, except for code loading that happens outside bootm.
-Scott
I do understand what it does, but I still don't get why it should be done, since precisely payload control transfer happens through bootm and the like which already properly flush cache.
Also, AFAIK U-Boot on multiple cores runs on a single core (possibly started from a smaller adjunct core) and will load and execute its payload on that same single core; the payload might enable and run additional cores if it so decides, but I don't know that U-Boot would start another main core. Still, I may have missed something.
Anyway:
Is there an ARM multi-core target in U-Boot where U-Boot runs on one core but its payload shall be started on another, "un-booted", core, and which experiences issues due to the first core not flushing cache? If no existing target needs this, then this patch is useless. If there exists such a target and issue, then the right fix is not a shell command, it is a programmatic flush before the other core is enabled, so that it always sees correct RAM.
Maybe this is some code that might come in handy for some future target not in U-Boot yes which will have the first core start a payload on another core? Then the previous argument applies (the fix should not be a shell command, it should be in source code), plus, the patch is dead code until and unless said target is also added in a single series.
Amicalement,