Updated numeric hexcodes with GENMASK macro in few spi drivers.
Signed-off-by: Jagan Teki jteki@openedev.com Cc: Tom Rini trini@konsulko.com Cc: Simon Glass sjg@chromium.org Cc: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Peng Fan Peng.Fan@freescale.com Cc: Stefan Roese sr@denx.de Cc: Marek Vasut marex@denx.de Cc: Stephen Warren swarren@nvidia.com Cc: Tom Warren twarren@nvidia.com Cc: Michal Simek michal.simek@xilinx.com Cc: Siva Durga Prasad Paladugu sivadur@xilinx.com --- drivers/spi/atmel_spi.h | 2 +- drivers/spi/cadence_qspi_apb.c | 48 +++++++++++++++++++++--------------------- drivers/spi/designware_spi.c | 2 +- drivers/spi/fsl_qspi.c | 2 +- drivers/spi/mxs_spi.c | 2 +- drivers/spi/omap3_spi.h | 10 ++++----- drivers/spi/tegra114_spi.c | 12 +++++------ drivers/spi/tegra20_sflash.c | 2 +- drivers/spi/tegra20_slink.c | 4 ++-- drivers/spi/xilinx_spi.c | 14 ++++++------ drivers/spi/zynq_spi.c | 6 +++--- 11 files changed, 52 insertions(+), 52 deletions(-)
diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h index 5b892d2..76b8556 100644 --- a/drivers/spi/atmel_spi.h +++ b/drivers/spi/atmel_spi.h @@ -59,7 +59,7 @@ #define ATMEL_SPI_CSRx_CSAAT BIT(3) #define ATMEL_SPI_CSRx_BITS(x) ((x) << 4) #define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8) -#define ATMEL_SPI_CSRx_SCBR_MAX 0xff +#define ATMEL_SPI_CSRx_SCBR_MAX GENMASK(7, 0) #define ATMEL_SPI_CSRx_DLYBS(x) ((x) << 16) #define ATMEL_SPI_CSRx_DLYBCT(x) ((x) << 24)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index ff375e5..e376fc5 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -50,7 +50,7 @@ #define CQSPI_INST_TYPE_QUAD (2)
#define CQSPI_STIG_DATA_LEN_MAX (8) -#define CQSPI_INDIRECTTRIGGER_ADDR_MASK (0xFFFFF) +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK GENMASK(19, 0)
#define CQSPI_DUMMY_CLKS_PER_BYTE (8) #define CQSPI_DUMMY_BYTES_MAX (4) @@ -71,8 +71,8 @@ #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 #define CQSPI_REG_CONFIG_BAUD_LSB 19 #define CQSPI_REG_CONFIG_IDLE_LSB 31 -#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF -#define CQSPI_REG_CONFIG_BAUD_MASK 0xF +#define CQSPI_REG_CONFIG_CHIPSELECT_MASK GENMASK(3, 0) +#define CQSPI_REG_CONFIG_BAUD_MASK GENMASK(3, 0)
#define CQSPI_REG_RD_INSTR 0x04 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 @@ -81,10 +81,10 @@ #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 -#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 -#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 -#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 -#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F +#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK GENMASK(1, 0) +#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK GENMASK(1, 0) +#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK GENMASK(1, 0) +#define CQSPI_REG_RD_INSTR_DUMMY_MASK GENMASK(4, 0)
#define CQSPI_REG_WR_INSTR 0x08 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 @@ -94,23 +94,23 @@ #define CQSPI_REG_DELAY_TCHSH_LSB 8 #define CQSPI_REG_DELAY_TSD2D_LSB 16 #define CQSPI_REG_DELAY_TSHSL_LSB 24 -#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF -#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF -#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF -#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF +#define CQSPI_REG_DELAY_TSLCH_MASK GENMASK(7, 0) +#define CQSPI_REG_DELAY_TCHSH_MASK GENMASK(7, 0) +#define CQSPI_REG_DELAY_TSD2D_MASK GENMASK(7, 0) +#define CQSPI_REG_DELAY_TSHSL_MASK GENMASK(7, 0)
#define CQSPI_READLCAPTURE 0x10 #define CQSPI_READLCAPTURE_BYPASS_LSB 0 #define CQSPI_READLCAPTURE_DELAY_LSB 1 -#define CQSPI_READLCAPTURE_DELAY_MASK 0xF +#define CQSPI_READLCAPTURE_DELAY_MASK GENMASK(3, 0)
#define CQSPI_REG_SIZE 0x14 #define CQSPI_REG_SIZE_ADDRESS_LSB 0 #define CQSPI_REG_SIZE_PAGE_LSB 4 #define CQSPI_REG_SIZE_BLOCK_LSB 16 -#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF -#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF -#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F +#define CQSPI_REG_SIZE_ADDRESS_MASK GENMASK(3, 0) +#define CQSPI_REG_SIZE_PAGE_MASK GENMASK(11, 0) +#define CQSPI_REG_SIZE_BLOCK_MASK GENMASK(5, 0)
#define CQSPI_REG_SRAMPARTITION 0x18 #define CQSPI_REG_INDIRECTTRIGGER 0x1C @@ -121,8 +121,8 @@ #define CQSPI_REG_SDRAMLEVEL 0x2C #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 -#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF -#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF +#define CQSPI_REG_SDRAMLEVEL_RD_MASK GENMASK(15, 0) +#define CQSPI_REG_SDRAMLEVEL_WR_MASK GENMASK(15, 0)
#define CQSPI_REG_IRQSTATUS 0x40 #define CQSPI_REG_IRQMASK 0x44 @@ -148,11 +148,11 @@ #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 -#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F -#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 -#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 -#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 -#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF +#define CQSPI_REG_CMDCTRL_DUMMY_MASK GENMASK(4, 0) +#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK GENMASK(2, 0) +#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK GENMASK(1, 0) +#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK GENMASK(2, 0) +#define CQSPI_REG_CMDCTRL_OPCODE_MASK GENMASK(7, 0)
#define CQSPI_REG_INDIRECTWR 0x70 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) @@ -469,7 +469,7 @@ void cadence_qspi_apb_chipselect(void *reg_base, * CS2 to 4b'1011 * CS3 to 4b'0111 */ - chip_select = 0xF & ~(1 << chip_select); + chip_select = GENMASK(3, 0) & ~(1 << chip_select); }
reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK @@ -726,7 +726,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD) writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT); #else - writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT); + writel(GENMASK(7, 0), plat->regbase + CQSPI_REG_MODE_BIT); #endif
/* Convert to clock cycles. */ diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 18f9786..d0733ee 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -74,7 +74,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_CFS_OFFSET 12
/* Bit fields in SR, 7 bits */ -#define SR_MASK 0x7f /* cover 7 bits */ +#define SR_MASK GENMASK(6, 0) /* cover 7 bits */ #define SR_BUSY BIT(0) #define SR_TF_NOT_FULL BIT(1) #define SR_TF_EMPT BIT(2) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index e1a0ec9..10733df 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; #define TX_BUFFER_SIZE 0x40 #endif
-#define OFFSET_BITS_MASK 0x00ffffff +#define OFFSET_BITS_MASK GENMASK(24, 0)
#define FLASH_STATUS_WEL 0x02
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index 2b9f395..270d0e6 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -22,7 +22,7 @@
#define MXS_SPI_MAX_TIMEOUT 1000000 #define MXS_SPI_PORT_OFFSET 0x2000 -#define MXS_SSP_CHIPSELECT_MASK 0x00300000 +#define MXS_SSP_CHIPSELECT_MASK GENMASK(21, 20) #define MXS_SSP_CHIPSELECT_SHIFT 20
#define MXSSSP_SMALL_TRANSFER 512 diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h index 269a5c7..20276b7 100644 --- a/drivers/spi/omap3_spi.h +++ b/drivers/spi/omap3_spi.h @@ -64,12 +64,12 @@ struct mcspi {
#define OMAP3_MCSPI_CHCONF_PHA BIT(0) #define OMAP3_MCSPI_CHCONF_POL BIT(1) -#define OMAP3_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) +#define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2) #define OMAP3_MCSPI_CHCONF_EPOL BIT(6) -#define OMAP3_MCSPI_CHCONF_WL_MASK (0x1f << 7) -#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12) -#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12) -#define OMAP3_MCSPI_CHCONF_TRM_MASK (0x03 << 12) +#define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7) +#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) +#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) +#define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12) #define OMAP3_MCSPI_CHCONF_DMAW BIT(14) #define OMAP3_MCSPI_CHCONF_DMAR BIT(15) #define OMAP3_MCSPI_CHCONF_DPE0 BIT(16) diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c index 61a0ecf..48877c3 100644 --- a/drivers/spi/tegra114_spi.c +++ b/drivers/spi/tegra114_spi.c @@ -35,9 +35,9 @@ DECLARE_GLOBAL_DATA_PTR; /* COMMAND1 */ #define SPI_CMD1_GO BIT(31) #define SPI_CMD1_M_S BIT(30) -#define SPI_CMD1_MODE_MASK 0x3 +#define SPI_CMD1_MODE_MASK GENMASK(1, 0) #define SPI_CMD1_MODE_SHIFT 28 -#define SPI_CMD1_CS_SEL_MASK 0x3 +#define SPI_CMD1_CS_SEL_MASK GENMASK(1, 0) #define SPI_CMD1_CS_SEL_SHIFT 26 #define SPI_CMD1_CS_POL_INACTIVE3 BIT(25) #define SPI_CMD1_CS_POL_INACTIVE2 BIT(24) @@ -45,7 +45,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_CMD1_CS_POL_INACTIVE0 BIT(22) #define SPI_CMD1_CS_SW_HW BIT(21) #define SPI_CMD1_CS_SW_VAL BIT(20) -#define SPI_CMD1_IDLE_SDA_MASK 0x3 +#define SPI_CMD1_IDLE_SDA_MASK GENMASK(1, 0) #define SPI_CMD1_IDLE_SDA_SHIFT 18 #define SPI_CMD1_BIDIR BIT(17) #define SPI_CMD1_LSBI_FE BIT(16) @@ -55,14 +55,14 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_CMD1_RX_EN BIT(12) #define SPI_CMD1_TX_EN BIT(11) #define SPI_CMD1_PACKED BIT(5) -#define SPI_CMD1_BIT_LEN_MASK 0x1F +#define SPI_CMD1_BIT_LEN_MASK GENMASK(4, 0) #define SPI_CMD1_BIT_LEN_SHIFT 0
/* COMMAND2 */ #define SPI_CMD2_TX_CLK_TAP_DELAY BIT(6) -#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6) +#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11, 6) #define SPI_CMD2_RX_CLK_TAP_DELAY BIT(0) -#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0) +#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5, 0)
/* TRANSFER STATUS */ #define SPI_XFER_STS_RDY BIT(30) diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c index 4d3f1e4..77d638b 100644 --- a/drivers/spi/tegra20_sflash.c +++ b/drivers/spi/tegra20_sflash.c @@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_CMD_CS1_EN BIT(6) #define SPI_CMD_CS0_EN BIT(5) #define SPI_CMD_BIT_LENGTH BIT(4) -#define SPI_CMD_BIT_LENGTH_MASK 0x0000001F +#define SPI_CMD_BIT_LENGTH_MASK GENMASK(4, 0)
#define SPI_STAT_BSY BIT(31) #define SPI_STAT_RDY BIT(30) diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c index 674c7ab..427a2d6 100644 --- a/drivers/spi/tegra20_slink.c +++ b/drivers/spi/tegra20_slink.c @@ -41,13 +41,13 @@ DECLARE_GLOBAL_DATA_PTR; #define SLINK_CMD_CS_VAL BIT(12) #define SLINK_CMD_CS_SOFT BIT(11) #define SLINK_CMD_BIT_LENGTH BIT(4) -#define SLINK_CMD_BIT_LENGTH_MASK 0x0000001F +#define SLINK_CMD_BIT_LENGTH_MASK GENMASK(4, 0) /* COMMAND2 */ #define SLINK_CMD2_TXEN BIT(30) #define SLINK_CMD2_RXEN BIT(31) #define SLINK_CMD2_SS_EN BIT(18) #define SLINK_CMD2_SS_EN_SHIFT 18 -#define SLINK_CMD2_SS_EN_MASK 0x000C0000 +#define SLINK_CMD2_SS_EN_MASK GENMASK(19, 18) #define SLINK_CMD2_CS_ACTIVE_BETWEEN BIT(17) /* STATUS */ #define SLINK_STAT_BSY BIT(31) diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 992a95a..58ef1fa 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -52,14 +52,14 @@ #define SPISR_RX_EMPTY BIT(0)
/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */ -#define SPIDTR_8BIT_MASK (0xff << 0) -#define SPIDTR_16BIT_MASK (0xffff << 0) -#define SPIDTR_32BIT_MASK (0xffffffff << 0) +#define SPIDTR_8BIT_MASK GENMASK(7, 0) +#define SPIDTR_16BIT_MASK GENMASK(15, 0) +#define SPIDTR_32BIT_MASK GENMASK(31, 0)
/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */ -#define SPIDRR_8BIT_MASK (0xff << 0) -#define SPIDRR_16BIT_MASK (0xffff << 0) -#define SPIDRR_32BIT_MASK (0xffffffff << 0) +#define SPIDRR_8BIT_MASK GENMASK(7, 0) +#define SPIDRR_16BIT_MASK GENMASK(15, 0) +#define SPIDRR_32BIT_MASK GENMASK(31, 0)
/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */ #define SPISSR_MASK(cs) (1 << (cs)) @@ -75,7 +75,7 @@ #define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
#ifndef CONFIG_XILINX_SPI_IDLE_VAL -#define CONFIG_XILINX_SPI_IDLE_VAL 0xff +#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0) #endif
#ifndef CONFIG_SYS_XILINX_SPI_LIST diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index 9e48770..861125e 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -22,14 +22,14 @@ DECLARE_GLOBAL_DATA_PTR; /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */ #define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */ #define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */ -#define ZYNQ_SPI_CR_CS_MASK (0xF << 10) /* Chip select */ -#define ZYNQ_SPI_CR_BRD_MASK (0x7 << 3) /* Baud rate div */ +#define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */ +#define ZYNQ_SPI_CR_BRD_MASK GENMASK(5, 3) /* Baud rate div */ #define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */ #define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */ #define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */ #define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */ #define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ -#define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */ +#define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ #define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
#define ZYNQ_SPI_FIFO_DEPTH 128