On Jul 17, 2009, at 10:14 AM, Peter Tyser wrote:
Previously, 85xx and 86xx boards would display DRAM information on bootup such as:
... I2C: ready DRAM: Memory controller interleaving enabled: Bank interleaving! 2 GB FLASH: 256 MB ...
This patch moves the printing of the DRAM controller configuration to a common board_add_ram_info() function which prints out DDR type, width, CAS latency, and ECC mode. It also makes the DDR interleaving information print out in a more sane manner:
... I2C: ready DRAM: 2 GB (DDR2, 64-bit, CL=4, ECC on) DDR Controller Interleaving Mode: bank FLASH: 256 MB ...
Signed-off-by: Peter Tyser ptyser@xes-inc.com
cpu/mpc8xxx/ddr/main.c | 43 +-------------------- cpu/mpc8xxx/ddr/util.c | 96 +++++++++++++++++++++++++++++++++++++++ +++++++++ 2 files changed, 98 insertions(+), 41 deletions(-)
applied
- k