Remove remaining legacy NAND defines for Beagle, EVM, Overo and Pandora.
Signed-off-by: Dirk Behme dirk.behme@googlemail.com ---
For Zoom1 it was already removed by
http://lists.denx.de/pipermail/u-boot/2009-April/050150.html http://lists.denx.de/pipermail/u-boot/2009-April/050871.html
Changes in v2:
- Remove even more legacy NAND defines. Thanks to Tom Rix for the hint.
This version v2 makes all previous versions of this patch obsolete.
include/configs/omap3_beagle.h | 29 ----------------------------- include/configs/omap3_evm.h | 29 ----------------------------- include/configs/omap3_overo.h | 30 ------------------------------ include/configs/omap3_pandora.h | 29 ----------------------------- 4 files changed, 117 deletions(-)
Index: u-boot-main/include/configs/omap3_beagle.h =================================================================== --- u-boot-main.orig/include/configs/omap3_beagle.h +++ u-boot-main/include/configs/omap3_beagle.h @@ -135,18 +135,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -#define SECTORSIZE 512 - -#define NAND_ALLOW_ERASE_ALL -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 -#define NAND_NO_RB 1 -#define CONFIG_SYS_NAND_WP
#define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ @@ -306,21 +294,4 @@ extern unsigned int boot_flash_sec; extern unsigned int boot_flash_type; #endif
- -#define WRITE_NAND_COMMAND(d, adr)\ - writel(d, &nand_cs_base->nand_cmd) -#define WRITE_NAND_ADDRESS(d, adr)\ - writel(d, &nand_cs_base->nand_adr) -#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) -#define READ_NAND(adr) readl(&nand_cs_base->nand_dat) - -/* Other NAND Access APIs */ -#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ - while (0) -#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ - while (0) -#define NAND_DISABLE_CE(nand) -#define NAND_ENABLE_CE(nand) -#define NAND_WAIT_READY(nand) udelay(10) - #endif /* __CONFIG_H */ Index: u-boot-main/include/configs/omap3_evm.h =================================================================== --- u-boot-main.orig/include/configs/omap3_evm.h +++ u-boot-main/include/configs/omap3_evm.h @@ -133,18 +133,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ /* NAND devices */ -#define SECTORSIZE 512 - -#define NAND_ALLOW_ERASE_ALL -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 -#define NAND_NO_RB 1 -#define CONFIG_SYS_NAND_WP
#define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ @@ -299,23 +287,6 @@ extern unsigned int boot_flash_sec; extern unsigned int boot_flash_type; #endif
- -#define WRITE_NAND_COMMAND(d, adr)\ - writel(d, &nand_cs_base->nand_cmd) -#define WRITE_NAND_ADDRESS(d, adr)\ - writel(d, &nand_cs_base->nand_adr) -#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) -#define READ_NAND(adr) readl(&nand_cs_base->nand_dat) - -/* Other NAND Access APIs */ -#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ - while (0) -#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ - while (0) -#define NAND_DISABLE_CE(nand) -#define NAND_ENABLE_CE(nand) -#define NAND_WAIT_READY(nand) udelay(10) - /*---------------------------------------------------------------------------- * SMSC9115 Ethernet from SMSC9118 family *---------------------------------------------------------------------------- Index: u-boot-main/include/configs/omap3_overo.h =================================================================== --- u-boot-main.orig/include/configs/omap3_overo.h +++ u-boot-main/include/configs/omap3_overo.h @@ -122,19 +122,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -#define SECTORSIZE 512 - -#define NAND_ALLOW_ERASE_ALL -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 -#define NAND_NO_RB 1 -#define CONFIG_SYS_NAND_WP - #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ #define CONFIG_JFFS2_DEV "nand0" @@ -293,21 +280,4 @@ extern unsigned int boot_flash_sec; extern unsigned int boot_flash_type; #endif
- -#define WRITE_NAND_COMMAND(d, adr)\ - writel(d, &nand_cs_base->nand_cmd) -#define WRITE_NAND_ADDRESS(d, adr)\ - writel(d, &nand_cs_base->nand_adr) -#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) -#define READ_NAND(adr) readl(&nand_cs_base->nand_dat) - -/* Other NAND Access APIs */ -#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ - while (0) -#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ - while (0) -#define NAND_DISABLE_CE(nand) -#define NAND_ENABLE_CE(nand) -#define NAND_WAIT_READY(nand) udelay(10) - #endif /* __CONFIG_H */ Index: u-boot-main/include/configs/omap3_pandora.h =================================================================== --- u-boot-main.orig/include/configs/omap3_pandora.h +++ u-boot-main/include/configs/omap3_pandora.h @@ -125,18 +125,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -#define SECTORSIZE 512 - -#define NAND_ALLOW_ERASE_ALL -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 -#define NAND_NO_RB 1 -#define CONFIG_SYS_NAND_WP
#define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ @@ -295,21 +283,4 @@ extern unsigned int boot_flash_sec; extern unsigned int boot_flash_type; #endif
- -#define WRITE_NAND_COMMAND(d, adr)\ - writel(d, &nand_cs_base->nand_cmd) -#define WRITE_NAND_ADDRESS(d, adr)\ - writel(d, &nand_cs_base->nand_adr) -#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) -#define READ_NAND(adr) readl(&nand_cs_base->nand_dat) - -/* Other NAND Access APIs */ -#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ - while (0) -#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ - while (0) -#define NAND_DISABLE_CE(nand) -#define NAND_ENABLE_CE(nand) -#define NAND_WAIT_READY(nand) udelay(10) - #endif /* __CONFIG_H */