On 5/13/20 2:23 PM, Patrick DELAUNAY wrote:
Hi Marek,
From: Marek Vasut marex@denx.de Sent: mercredi 13 mai 2020 12:53
On 5/13/20 11:12 AM, Patrick DELAUNAY wrote:
Dear Marek,
From: Marek Vasut marex@denx.de Sent: mardi 12 mai 2020 19:07
There are two speed grades of the STM32MP1, the A/C and D/F, the former can run up to 650 MHz, the later at up to 800 MHz. Allow specifying PLL config for both in the DT, so that it is possible to cater for boards which can be populated with either SoC.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
drivers/clk/clk_stm32mp1.c | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-)
[...]
The 2 speed grade will be supported with OPP information and HW support,present in kernel device tree (upstream in progress)
I port this patch in U-Boot with: http://patchwork.ozlabs.org/project/uboot/patch/20200421171123.2.Id362 0aec4deb419f1c1a5876b865556e86d3aba1@changeid/
Please check the full serie stm32mp1: use OPP information for PLL1 settings in SPL http://patchwork.ozlabs.org/project/uboot/list/?series=171767
PLL1 settings are now computed in SPL and no more read from DT.
That's even better, nice, thanks !
btw. does the D/F 800 MHz always set BIT(7) in the CPU ID , while the A/C 650 MHz part never does ? Maybe you can use that to discern the speed grades instead of listing all the parts ...
Yes but the meaning of RPN (the part of CPU IP) is undocumented... And BIT(7) could be no more be valid for next products.
So I prefer use the documented value of Device Part Number (RPN) as a fixed value.
For example:
Bits 7:0 RPN_coding[7:0]: 0x00: STM32MP157Cx 0x01: STM32MP157Ax 0x80: STM32MP157Fx 0x81: STM32MP157Dx Others: Reserved
And it is also requested by ST marketing team (don't code on RPN bit decoding).
Even if I agree: it is more elegant than my switch case.
And it saves a few bytes in SPL size ;-)