Andre Schwarz andre.schwarz@matrix-vision.de wrote on 2010/11/04 15:49:06:
Jocke,
CPU: e300c4, MPC8379, Rev: 2.1 at 600 MHz, CSB: 400 MHz
- Boot from NOR Flash
- HRCW from I2C EEPROM
- Reset Vector 0x100, i.e. low boot.
OK, almost the same as me, but I got a: CPU: e300c2, MPC8321, Rev: 1.1 at 266.664 MHz, CSB: 133.332 MHz
However, I think I just found the problem.
excellent !
My tree is a bit messy now so no patch but it will be:
Stick an isync (or sync) in map_flash_by_law1 .... stw r4, LBLAWAR1(r3) /* LBLAWAR1<= 8MB Flash Size */ isync //HERE !! HERE !! HERE blr
ok - works for me, i.e. no quad-nop needed anymore.
Does both your boards work now?
I am guessing it takes a while for the stw r4, LBLAWAR1(r3) to hit the HW so one must wait for it, not sure what is best though, sync or isync?
If it is a timing issue why should have the nops influenced this ? I still wonder if this is the real problem and whether we might need more (i)syncs elsewhere ...
You can try replacing the isync with 4 nops. That works for me. moving the 4 nops after the blr doesn't work.
I think it worked earlier by chance but the removal of the flags changed timing, probably a cache line crossing at the wrong place.
Jocke