Drops the CONFIG_SYS_
Signed-off-by: Martha Marx mmarx@silicontkx.com --- board/ads5121/ads5121.c | 138 ++++++++++++++++++++++---------------------- include/configs/ads5121.h | 104 +++++++++++++++++----------------- 2 files changed, 121 insertions(+), 121 deletions(-)
diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 1983492..306f184 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -153,32 +153,32 @@ long int fixed_sdram (void) __asm__ __volatile__ ("isync");
/* Enable DDR */ - im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_EN; + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_EN;
/* Initialize DDR Priority Manager */ - im->mddrc.prioman_config1 = CONFIG_SYS_MDDRCGRP_PM_CFG1; - im->mddrc.prioman_config2 = CONFIG_SYS_MDDRCGRP_PM_CFG2; - im->mddrc.hiprio_config = CONFIG_SYS_MDDRCGRP_HIPRIO_CFG; - im->mddrc.lut_table0_main_upper = CONFIG_SYS_MDDRCGRP_LUT0_MU; - im->mddrc.lut_table0_main_lower = CONFIG_SYS_MDDRCGRP_LUT0_ML; - im->mddrc.lut_table1_main_upper = CONFIG_SYS_MDDRCGRP_LUT1_MU; - im->mddrc.lut_table1_main_lower = CONFIG_SYS_MDDRCGRP_LUT1_ML; - im->mddrc.lut_table2_main_upper = CONFIG_SYS_MDDRCGRP_LUT2_MU; - im->mddrc.lut_table2_main_lower = CONFIG_SYS_MDDRCGRP_LUT2_ML; - im->mddrc.lut_table3_main_upper = CONFIG_SYS_MDDRCGRP_LUT3_MU; - im->mddrc.lut_table3_main_lower = CONFIG_SYS_MDDRCGRP_LUT3_ML; - im->mddrc.lut_table4_main_upper = CONFIG_SYS_MDDRCGRP_LUT4_MU; - im->mddrc.lut_table4_main_lower = CONFIG_SYS_MDDRCGRP_LUT4_ML; - im->mddrc.lut_table0_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT0_AU; - im->mddrc.lut_table0_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT0_AL; - im->mddrc.lut_table1_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT1_AU; - im->mddrc.lut_table1_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT1_AL; - im->mddrc.lut_table2_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT2_AU; - im->mddrc.lut_table2_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT2_AL; - im->mddrc.lut_table3_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT3_AU; - im->mddrc.lut_table3_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT3_AL; - im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU; - im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL; + im->mddrc.prioman_config1 = MDDRCGRP_PM_CFG1; + im->mddrc.prioman_config2 = MDDRCGRP_PM_CFG2; + im->mddrc.hiprio_config = MDDRCGRP_HIPRIO_CFG; + im->mddrc.lut_table0_main_upper = MDDRCGRP_LUT0_MU; + im->mddrc.lut_table0_main_lower = MDDRCGRP_LUT0_ML; + im->mddrc.lut_table1_main_upper = MDDRCGRP_LUT1_MU; + im->mddrc.lut_table1_main_lower = MDDRCGRP_LUT1_ML; + im->mddrc.lut_table2_main_upper = MDDRCGRP_LUT2_MU; + im->mddrc.lut_table2_main_lower = MDDRCGRP_LUT2_ML; + im->mddrc.lut_table3_main_upper = MDDRCGRP_LUT3_MU; + im->mddrc.lut_table3_main_lower = MDDRCGRP_LUT3_ML; + im->mddrc.lut_table4_main_upper = MDDRCGRP_LUT4_MU; + im->mddrc.lut_table4_main_lower = MDDRCGRP_LUT4_ML; + im->mddrc.lut_table0_alternate_upper = MDDRCGRP_LUT0_AU; + im->mddrc.lut_table0_alternate_lower = MDDRCGRP_LUT0_AL; + im->mddrc.lut_table1_alternate_upper = MDDRCGRP_LUT1_AU; + im->mddrc.lut_table1_alternate_lower = MDDRCGRP_LUT1_AL; + im->mddrc.lut_table2_alternate_upper = MDDRCGRP_LUT2_AU; + im->mddrc.lut_table2_alternate_lower = MDDRCGRP_LUT2_AL; + im->mddrc.lut_table3_alternate_upper = MDDRCGRP_LUT3_AU; + im->mddrc.lut_table3_alternate_lower = MDDRCGRP_LUT3_AL; + im->mddrc.lut_table4_alternate_upper = MDDRCGRP_LUT4_AU; + im->mddrc.lut_table4_alternate_lower = MDDRCGRP_LUT4_AL;
if (brd_rev >= 0x0400 && (mac = getenv("ethaddr"))) { for (i=0; i<6; i++) { @@ -201,70 +201,70 @@ long int fixed_sdram (void)
/* Initialize MDDRC */ if (use_micron) { - im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_MICRON; - im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0; - im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_MICRON; - im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_MICRON; + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_MICRON; + im->mddrc.ddr_time_config0 = MDDRC_TIME_CFG0; + im->mddrc.ddr_time_config1 = MDDRC_TIME_CFG1_MICRON; + im->mddrc.ddr_time_config2 = MDDRC_TIME_CFG2_MICRON; } else { - im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA; - im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0; - im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA; - im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA; + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_ELPIDA; + im->mddrc.ddr_time_config0 = MDDRC_TIME_CFG0; + im->mddrc.ddr_time_config1 = MDDRC_TIME_CFG1_ELPIDA; + im->mddrc.ddr_time_config2 = MDDRC_TIME_CFG2_ELPIDA; }
/* Initialize DDR */ for (i = 0; i < 10; i++) - im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; + im->mddrc.ddr_command = DDR_NOP;
- im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; - im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; - im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; + im->mddrc.ddr_command = DDR_PCHG_ALL; + im->mddrc.ddr_command = DDR_NOP; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = DDR_NOP; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = DDR_NOP;
if (use_micron) { /* Micron init sequence */ - im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; - im->mddrc.ddr_command = CONFIG_SYS_DDR_EM2; - im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; - im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_DDR_EM2; - im->mddrc.ddr_command = CONFIG_SYS_DDR_EM3; - im->mddrc.ddr_command = CONFIG_SYS_DDR_EN_DLL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = DDR_NOP; + im->mddrc.ddr_command = DDR_EM2; + im->mddrc.ddr_command = DDR_NOP; + im->mddrc.ddr_command = DDR_PCHG_ALL; + im->mddrc.ddr_command = DDR_EM2; + im->mddrc.ddr_command = DDR_EM3; + im->mddrc.ddr_command = DDR_EN_DLL; + im->mddrc.ddr_command = MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = DDR_PCHG_ALL; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = MICRON_INIT_DEV_OP; udelay(200); } else { /* Elpida init sequence - works for Micron too but runs slower */ - im->mddrc.ddr_command = CONFIG_SYS_DDR_EM2; - im->mddrc.ddr_command = CONFIG_SYS_DDR_EM3; - im->mddrc.ddr_command = CONFIG_SYS_DDR_EN_DLL; - im->mddrc.ddr_command = CONFIG_SYS_DDR_RES_DLL; - im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_ELPIDA_INIT_DEV_OP; + im->mddrc.ddr_command = DDR_EM2; + im->mddrc.ddr_command = DDR_EM3; + im->mddrc.ddr_command = DDR_EN_DLL; + im->mddrc.ddr_command = DDR_RES_DLL; + im->mddrc.ddr_command = DDR_PCHG_ALL; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = ELPIDA_INIT_DEV_OP; udelay(200); } - im->mddrc.ddr_command = CONFIG_SYS_DDR_OCD_DEFAULT; - im->mddrc.ddr_command = CONFIG_SYS_DDR_OCD_EXIT; - im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; + im->mddrc.ddr_command = DDR_OCD_DEFAULT; + im->mddrc.ddr_command = DDR_OCD_EXIT; + im->mddrc.ddr_command = DDR_NOP; for (i = 0; i < 10; i++) - im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; + im->mddrc.ddr_command = DDR_NOP; /* Start MDDRC */ - im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN; + im->mddrc.ddr_time_config0 = MDDRC_TIME_CFG0_RUN;
if (use_micron) - im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_MICRON_RUN; + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_MICRON_RUN; else - im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA_RUN; + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_ELPIDA_RUN;
return msize; } diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index ab06276..3fe3c50 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -130,63 +130,63 @@ * [09:05] DRAM tRP: * [04:00] DRAM tRPA */ -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN ~(0x10000000) +#define MDDRC_SYS_CFG_RUN ~(0x10000000) #ifdef CONFIG_ADS5121_REV2 -#define CONFIG_SYS_MDDRC_SYS_CFG_MICRON 0xF8604A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1_MICRON 0x54EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2_MICRON 0x35210864 +#define MDDRC_SYS_CFG_MICRON 0xF8604A00 +#define MDDRC_TIME_CFG1_MICRON 0x54EC1168 +#define MDDRC_TIME_CFG2_MICRON 0x35210864 #else -#define CONFIG_SYS_MDDRC_SYS_CFG_MICRON 0xFA804A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_MICRON_RUN 0xEA804A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1_MICRON 0x68EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2_MICRON 0x34310864 +#define MDDRC_SYS_CFG_MICRON 0xFA804A00 +#define MDDRC_SYS_CFG_MICRON_RUN 0xEA804A00 +#define MDDRC_TIME_CFG1_MICRON 0x68EC1168 +#define MDDRC_TIME_CFG2_MICRON 0x34310864 #endif -#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xFA802b40 -#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA_RUN 0xEA802b40 -#define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189 -#define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35410864 - -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_SYS_CFG_CLK_BIT (1 << 29) -#define CONFIG_SYS_MDDRC_SYS_CFG_CKE_BIT (1 << 30) -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_ELPIDA_INIT_DEV_OP 0x01000842 -#define CONFIG_SYS_DDR_NOP 0x01380000 -#define CONFIG_SYS_DDR_PCHG_ALL 0x01100400 -#define CONFIG_SYS_DDR_EM2 0x01020000 -#define CONFIG_SYS_DDR_EM3 0x01030000 -#define CONFIG_SYS_DDR_EN_DLL 0x01010000 -#define CONFIG_SYS_DDR_RES_DLL 0x01000932 -#define CONFIG_SYS_DDR_RFSH 0x01080000 -#define CONFIG_SYS_DDR_OCD_DEFAULT 0x01010780 -#define CONFIG_SYS_DDR_OCD_EXIT 0x01010400 +#define MDDRC_SYS_CFG_ELPIDA 0xFA802b40 +#define MDDRC_SYS_CFG_ELPIDA_RUN 0xEA802b40 +#define MDDRC_TIME_CFG1_ELPIDA 0x690e1189 +#define MDDRC_TIME_CFG2_ELPIDA 0x35410864 + +#define MDDRC_SYS_CFG_EN 0xF0000000 +#define MDDRC_SYS_CFG_CLK_BIT (1 << 29) +#define MDDRC_SYS_CFG_CKE_BIT (1 << 30) +#define MDDRC_TIME_CFG0 0x00003D2E +#define MDDRC_TIME_CFG0_RUN 0x06183D2E +#define MICRON_INIT_DEV_OP 0x01000432 +#define ELPIDA_INIT_DEV_OP 0x01000842 +#define DDR_NOP 0x01380000 +#define DDR_PCHG_ALL 0x01100400 +#define DDR_EM2 0x01020000 +#define DDR_EM3 0x01030000 +#define DDR_EN_DLL 0x01010000 +#define DDR_RES_DLL 0x01000932 +#define DDR_RFSH 0x01080000 +#define DDR_OCD_DEFAULT 0x01010780 +#define DDR_OCD_EXIT 0x01010400
/* DDR Priority Manager Configuration */ -#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 -#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 -#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC -#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA -#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 -#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 -#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 +#define MDDRCGRP_PM_CFG1 0x00077777 +#define MDDRCGRP_PM_CFG2 0x00000000 +#define MDDRCGRP_HIPRIO_CFG 0x00000001 +#define MDDRCGRP_LUT0_MU 0xFFEEDDCC +#define MDDRCGRP_LUT0_ML 0xBBAAAAAA +#define MDDRCGRP_LUT1_MU 0x66666666 +#define MDDRCGRP_LUT1_ML 0x55555555 +#define MDDRCGRP_LUT2_MU 0x44444444 +#define MDDRCGRP_LUT2_ML 0x44444444 +#define MDDRCGRP_LUT3_MU 0x55555555 +#define MDDRCGRP_LUT3_ML 0x55555558 +#define MDDRCGRP_LUT4_MU 0x11111111 +#define MDDRCGRP_LUT4_ML 0x11111122 +#define MDDRCGRP_LUT0_AU 0xaaaaaaaa +#define MDDRCGRP_LUT0_AL 0xaaaaaaaa +#define MDDRCGRP_LUT1_AU 0x66666666 +#define MDDRCGRP_LUT1_AL 0x66666666 +#define MDDRCGRP_LUT2_AU 0x11111111 +#define MDDRCGRP_LUT2_AL 0x11111111 +#define MDDRCGRP_LUT3_AU 0x11111111 +#define MDDRCGRP_LUT3_AL 0x11111111 +#define MDDRCGRP_LUT4_AU 0x11111111 +#define MDDRCGRP_LUT4_AL 0x11111111
/* * NOR FLASH on the Local Bus