Hi,
On 01-09-16 09:57, Antoine Tenart wrote:
Introducing the ARM_GIC configuration option, use it to only use GIC specific code in ARM PSCI function when the SoC has a GIC.
Signed-off-by: Antoine Tenart antoine.tenart@free-electrons.com
AFAIK sunxi is not the only user of these files, so before you can do this you should also select ARM_GIC in the other users I believe.
Regards,
Hans
arch/arm/cpu/armv7/nonsec_virt.S | 6 ++++++ arch/arm/cpu/armv7/virt-v7.c | 38 ++++++++++++++++++++++++-------------- 2 files changed, 30 insertions(+), 14 deletions(-)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 95ce9387b83e..2a11d2e83b80 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -164,6 +164,7 @@ ENDPROC(_smp_pen)
- though, but we check this in C before calling this function.
*/ ENTRY(_nonsec_init) +#ifdef CONFIG_ARM_GIC get_gicd_addr r3
mvn r1, #0 @ all bits to 1 @@ -175,6 +176,7 @@ ENTRY(_nonsec_init) str r1, [r3, #GICC_CTLR] @ and clear all other bits mov r1, #0xff str r1, [r3, #GICC_PMR] @ set priority mask register +#endif
mrc p15, 0, r0, c1, c1, 2 movw r1, #0x3fff @@ -200,7 +202,11 @@ ENTRY(_nonsec_init) mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors isb
+#ifdef CONFIG_ARM_GIC mov r0, r3 @ return GICC address +#else
- mov r0, #0
+#endif bx lr ENDPROC(_nonsec_init)
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index d33e5c61a9c2..925201e3f690 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -82,22 +82,11 @@ void __weak smp_kick_all_cpus(void) kick_secondary_cpus_gic(gic_dist_addr); }
-__weak void psci_board_init(void) -{ -}
-int armv7_init_nonsec(void) +#ifdef CONFIG_ARM_GIC +static void psci_gic_setup() {
- unsigned int reg;
- unsigned itlinesnr, i; unsigned long gic_dist_addr;
- /* check whether the CPU supports the security extensions */
- reg = read_id_pfr1();
- if ((reg & 0xF0) == 0) {
printf("nonsec: Security extensions not implemented.\n");return -1;- }
unsigned itlinesnr, i;
/* the SCR register will be set directly in the monitor mode handler,
- according to the spec one should not tinker with it in secure state
@@ -122,6 +111,27 @@ int armv7_init_nonsec(void) */ for (i = 1; i <= itlinesnr; i++) writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i); +} +#endif
+__weak void psci_board_init(void) +{ +}
+int armv7_init_nonsec(void) +{
- unsigned int reg;
- /* check whether the CPU supports the security extensions */
- reg = read_id_pfr1();
- if ((reg & 0xF0) == 0) {
printf("nonsec: Security extensions not implemented.\n");return -1;- }
+#ifdef CONFIG_ARM_GIC
- psci_gic_setup();
+#endif
psci_board_init();