M5271 dynamic clock multiplier. It is currently fixed at 100MHz.
Allow the board header file to set their own multiplier and divider. Added the #define for the multiplier and divider to the cpu header file.
Signed-off-by: Richard Retanubun RichardRetanubun@RuggedCom.com --- cpu/mcf52x2/cpu_init.c | 7 +++++- include/asm-m68k/m5271.h | 53 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 57 insertions(+), 3 deletions(-)
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 66f9164..02f37ae 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -181,9 +181,14 @@ void cpu_init_f(void) /* FlexBus Chipselect */ init_fbcs();
+#ifdef CONFIG_SYS_MCF_SYNCR + /* Set clockspeed according to board header file */ + mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR); +#else /* Set clockspeed to 100MHz */ - mbar_writeShort(MCF_FMPLL_SYNCR, + mbar_writeLong(MCF_FMPLL_SYNCR, MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0)); +#endif while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ; }
diff --git a/include/asm-m68k/m5271.h b/include/asm-m68k/m5271.h index 7877616..1c38b32 100644 --- a/include/asm-m68k/m5271.h +++ b/include/asm-m68k/m5271.h @@ -37,8 +37,27 @@
#define MCF_FMPLL_SYNCR 0x120000 #define MCF_FMPLL_SYNSR 0x120004 + #define MCF_FMPLL_SYNCR_MFD(x) ((x&0x7)<<24) +#define CONFIG_SYS_MCF_SYNCR_MFD_4X 0x00000000 +#define CONFIG_SYS_MCF_SYNCR_MFD_6X 0x01000000 +#define CONFIG_SYS_MCF_SYNCR_MFD_8X 0x02000000 +#define CONFIG_SYS_MCF_SYNCR_MFD_10X 0x03000000 +#define CONFIG_SYS_MCF_SYNCR_MFD_12X 0x04000000 +#define CONFIG_SYS_MCF_SYNCR_MFD_14X 0x05000000 +#define CONFIG_SYS_MCF_SYNCR_MFD_16X 0x06000000 +#define CONFIG_SYS_MCF_SYNCR_MFD_18X 0x07000000 + #define MCF_FMPLL_SYNCR_RFD(x) ((x&0x7)<<19) +#define CONFIG_SYS_MCF_SYNCR_RFD_DIV1 0x00000000 +#define CONFIG_SYS_MCF_SYNCR_RFD_DIV2 0x00080000 +#define CONFIG_SYS_MCF_SYNCR_RFD_DIV4 0x00100000 +#define CONFIG_SYS_MCF_SYNCR_RFD_DIV8 0x00180000 +#define CONFIG_SYS_MCF_SYNCR_RFD_DIV16 0x00200000 +#define CONFIG_SYS_MCF_SYNCR_RFD_DIV32 0x00280000 +#define CONFIG_SYS_MCF_SYNCR_RFD_DIV64 0x00300000 +#define CONFIG_SYS_MCF_SYNCR_RFD_DIV128 0x00380000 + #define MCF_FMPLL_SYNSR_LOCK 0x8
#define MCF_WTM_WCR 0x140000 @@ -50,17 +69,47 @@ #define MCF_RCM_RCR_FRCRSTOUT 0x40 #define MCF_RCM_RCR_SOFTRST 0x80
+#define MCF_GPIO_PODR_ADDR 0x100000 +#define MCF_GPIO_PODR_DATAH 0x100001 +#define MCF_GPIO_PODR_DATAL 0x100002 +#define MCF_GPIO_PODR_BUSCTL 0x100003 +#define MCF_GPIO_PODR_BS 0x100004 +#define MCF_GPIO_PODR_CS 0x100005 +#define MCF_GPIO_PODR_SDRAM 0x100006 +#define MCF_GPIO_PODR_FECI2C 0x100007 +#define MCF_GPIO_PODR_UARTH 0x100008 +#define MCF_GPIO_PODR_UARTL 0x100009 +#define MCF_GPIO_PODR_QSPI 0x10000A +#define MCF_GPIO_PODR_TIMER 0x10000B + +#define MCF_GPIO_PDDR_ADDR 0x100010 +#define MCF_GPIO_PDDR_DATAH 0x100011 +#define MCF_GPIO_PDDR_DATAL 0x100012 +#define MCF_GPIO_PDDR_BUSCTL 0x100013 +#define MCF_GPIO_PDDR_BS 0x100014 +#define MCF_GPIO_PDDR_CS 0x100015 +#define MCF_GPIO_PDDR_SDRAM 0x100016 +#define MCF_GPIO_PDDR_FECI2C 0x100017 +#define MCF_GPIO_PDDR_UARTH 0x100018 +#define MCF_GPIO_PDDR_UARTL 0x100019 +#define MCF_GPIO_PDDR_QSPI 0x10001A +#define MCF_GPIO_PDDR_TIMER 0x10001B + #define MCF_GPIO_PAR_AD 0x100040 +#define MCF_GPIO_PAR_BUSCTL 0x100042 +#define MCF_GPIO_PAR_BS 0x100044 #define MCF_GPIO_PAR_CS 0x100045 #define MCF_GPIO_PAR_SDRAM 0x100046 #define MCF_GPIO_PAR_FECI2C 0x100047 #define MCF_GPIO_PAR_UART 0x100048 +#define MCF_GPIO_PAR_QSPI 0x10004A +#define MCF_GPIO_PAR_TIMER 0x10004C
#define MCF_CCM_CIR 0x11000A #define MCF_CCM_CIR_PRN_MASK 0x3F #define MCF_CCM_CIR_PIN_LEN 6 -#define MCF_CCM_CIR_PIN_MCF5270 0x2e -#define MCF_CCM_CIR_PIN_MCF5271 0x80 +#define MCF_CCM_CIR_PIN_MCF5270 0x002e +#define MCF_CCM_CIR_PIN_MCF5271 0x0032
#define MCF_GPIO_AD_ADDR23 0x80 #define MCF_GPIO_AD_ADDR22 0x40