From: Zhong Hongbo bocui107@gmail.com
Signed-off-by: Zhong Hongbo bocui107@gmail.com --- Change for V4: - None. Change for V3: - Replace the magic numbers with variable name. - Use C language to implement memory initialization. Change for V2: - None. --- arch/arm/include/asm/arch-s3c64xx/dmc.h | 62 +++++++++ arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 178 +-------------------------- board/samsung/smdk6400/Makefile | 3 +- board/samsung/smdk6400/dmc_init.c | 110 +++++++++++++++++ board/samsung/smdk6400/lowlevel_init.S | 2 +- board/samsung/smdk6400/mem_init.S | 135 -------------------- board/samsung/smdk6400/setup.h | 85 +++++++++++++ 7 files changed, 265 insertions(+), 310 deletions(-) create mode 100644 arch/arm/include/asm/arch-s3c64xx/dmc.h create mode 100644 board/samsung/smdk6400/dmc_init.c delete mode 100644 board/samsung/smdk6400/mem_init.S
diff --git a/arch/arm/include/asm/arch-s3c64xx/dmc.h b/arch/arm/include/asm/arch-s3c64xx/dmc.h new file mode 100644 index 0000000..758e750 --- /dev/null +++ b/arch/arm/include/asm/arch-s3c64xx/dmc.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2012 + * Zhong Hongbo bocui107@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#ifndef __ASM_ARCH_DMC_H__ +#define __ASM_ARCH_DMC_H__ + +#ifndef __ASSEMBLY__ + +struct s3c64xx_dmc { + unsigned int memstat; + unsigned int memcmd; + unsigned int directcmd; + unsigned int memcfg; + unsigned int refresh; + unsigned int caslat; + unsigned int t_dqss; + unsigned int t_mrd; + unsigned int t_ras; + unsigned int t_rc; + unsigned int t_rcd; + unsigned int t_rfc; + unsigned int t_rp; + unsigned int t_rrd; + unsigned int t_wr; + unsigned int t_wtr; + unsigned int t_xp; + unsigned int t_xsr; + unsigned int t_esr; + unsigned int memcfg2; +#if defined(CONFIG_S3C6410) + unsigned int memcfg3; + unsigned char res1[0xac]; +#else + unsigned char res1[0xb0]; +#endif + unsigned int id_0_cfg[16]; + unsigned char res2[0xc0]; + unsigned int chip_0_cfg; + unsigned int chip_1_cfg; + unsigned char res3[0xf8]; + unsigned int user_status; + unsigned int user_config; +}; +#endif +#endif diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h index 1da327a..45a8918 100644 --- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h +++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h @@ -41,191 +41,18 @@ #include <asm/hardware.h>
#define ELFIN_CLOCK_POWER_BASE 0x7e00f000 - -/* - * GPIO - */ #define ELFIN_GPIO_BASE 0x7f008000 - -/* - * Bus Matrix - */ #define ELFIN_MEM_SYS_CFG 0x7e00f120 - -#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12) - -#define S3C64XX_MEM_SYS_CFG_NAND 0x0008 - -/* - * Memory controller - */ #define ELFIN_SROM_BASE 0x70000000 - -/* - * SDRAM Controller - */ #define ELFIN_DMC0_BASE 0x7e000000 #define ELFIN_DMC1_BASE 0x7e001000 - -#define INDEX_DMC_MEMC_STATUS 0x00 -#define INDEX_DMC_MEMC_CMD 0x04 -#define INDEX_DMC_DIRECT_CMD 0x08 -#define INDEX_DMC_MEMORY_CFG 0x0C -#define INDEX_DMC_REFRESH_PRD 0x10 -#define INDEX_DMC_CAS_LATENCY 0x14 -#define INDEX_DMC_T_DQSS 0x18 -#define INDEX_DMC_T_MRD 0x1C -#define INDEX_DMC_T_RAS 0x20 -#define INDEX_DMC_T_RC 0x24 -#define INDEX_DMC_T_RCD 0x28 -#define INDEX_DMC_T_RFC 0x2C -#define INDEX_DMC_T_RP 0x30 -#define INDEX_DMC_T_RRD 0x34 -#define INDEX_DMC_T_WR 0x38 -#define INDEX_DMC_T_WTR 0x3C -#define INDEX_DMC_T_XP 0x40 -#define INDEX_DMC_T_XSR 0x44 -#define INDEX_DMC_T_ESR 0x48 -#define INDEX_DMC_MEMORY_CFG2 0x4C -#define INDEX_DMC_CHIP_0_CFG 0x200 -#define INDEX_DMC_CHIP_1_CFG 0x204 -#define INDEX_DMC_CHIP_2_CFG 0x208 -#define INDEX_DMC_CHIP_3_CFG 0x20C -#define INDEX_DMC_USER_STATUS 0x300 -#define INDEX_DMC_USER_CONFIG 0x304 - -/* - * Memory Chip direct command - */ -#define DMC_NOP0 0x0c0000 -#define DMC_NOP1 0x1c0000 -#define DMC_PA0 0x000000 /* Precharge all */ -#define DMC_PA1 0x100000 -#define DMC_AR0 0x040000 /* Autorefresh */ -#define DMC_AR1 0x140000 -#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */ -#define DMC_SDR_MR1 0x180032 -#define DMC_DDR_MR0 0x080162 -#define DMC_DDR_MR1 0x180162 -#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */ -#define DMC_mDDR_MR1 0x180032 -#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */ -#define DMC_mSDR_EMR1 0x1a0000 -#define DMC_DDR_EMR0 0x090000 -#define DMC_DDR_EMR1 0x190000 -#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */ -#define DMC_mDDR_EMR1 0x1a0000 - -/* - * Definitions for memory configuration - * Set memory configuration - * active_chips = 1'b0 (1 chip) - * qos_master_chip = 3'b000(ARID[3:0]) - * memory burst = 3'b010(burst 4) - * stop_mem_clock = 1'b0(disable dynamical stop) - * auto_power_down = 1'b0(disable auto power-down mode) - * power_down_prd = 6'b00_0000(0 cycle for auto power-down) - * ap_bit = 1'b0 (bit position of auto-precharge is 10) - * row_bits = 3'b010(# row address 13) - * column_bits = 3'b010(# column address 10 ) - * - * Set user configuration - * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR - * - * Set chip select for chip [n] - * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff - * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24] - */ - -/* - * Nand flash controller - */ #define ELFIN_NAND_BASE 0x70200000 - -/* - * Interrupt - */ #define ELFIN_VIC0_BASE_ADDR 0x71200000 #define ELFIN_VIC1_BASE_ADDR 0x71300000 - -/* - * Watchdog timer - */ #define ELFIN_WATCHDOG_BASE 0x7E004000 - -/* - * UART - */ #define ELFIN_UART_BASE 0x7F005000 - -/* - * PWM timer - */ #define ELFIN_TIMER_BASE 0x7F006000
-/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define DMC1_MEM_CFG 0x00010012 /* burst 4, 13-bit row, 10-bit col */ -#define DMC1_MEM_CFG2 0xB45 -#define DMC1_CHIP0_CFG 0x150F8 /* 0x5000_0000~0x57ff_ffff (128 MiB) */ -#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */ - -/* Memory Parameters */ -/* DDR Parameters */ -#define DDR_tREFRESH 7800 /* ns */ -#define DDR_tRAS 45 /* ns (min: 45ns)*/ -#define DDR_tRC 68 /* ns (min: 67.5ns)*/ -#define DDR_tRCD 23 /* ns (min: 22.5ns)*/ -#define DDR_tRFC 80 /* ns (min: 80ns)*/ -#define DDR_tRP 23 /* ns (min: 22.5ns)*/ -#define DDR_tRRD 15 /* ns (min: 15ns)*/ -#define DDR_tWR 15 /* ns (min: 15ns)*/ -#define DDR_tXSR 120 /* ns (min: 120ns)*/ -#define DDR_CASL 3 /* CAS Latency 3 */ - -/* - * mDDR memory configuration - */ - -#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000) - -#define DMC_DDR_BA_EMRS 2 -#define DMC_DDR_MEM_CASLAT 3 -/* 6 Set Cas Latency to 3 */ -#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1) -/* Min 0.75 ~ 1.25 */ -#define DMC_DDR_t_DQSS 1 -/* Min 2 tck */ -#define DMC_DDR_t_MRD 2 -/* 7, Min 45ns */ -#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1) -/* 10, Min 67.5ns */ -#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1) -/* 4,5(TRM), Min 22.5ns */ -#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1) -#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3) -/* 11,18(TRM) Min 80ns */ -#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1) -#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5) -/* 4, 5(TRM) Min 22.5ns */ -#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1) -#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3) -/* 3, Min 15ns */ -#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1) -/* Min 15ns */ -#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1) -#define DMC_DDR_t_WTR 2 -/* 1tck + tIS(1.5ns) */ -#define DMC_DDR_t_XP 2 -/* 17, Min 120ns */ -#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1) -#define DMC_DDR_t_ESR DMC_DDR_t_XSR -/* TRM 2656 */ -#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH)) -/* 2b01 : mDDR */ -#define DMC_DDR_USER_CONFIG 1 - #ifndef __ASSEMBLY__
static inline unsigned long s3c64xx_get_base_uart(void) @@ -252,6 +79,11 @@ static inline unsigned long s3c64xx_get_base_clock(void) { return ELFIN_CLOCK_POWER_BASE; } + +static inline unsigned long s3c64xx_get_base_dmc1(void) +{ + return ELFIN_DMC1_BASE; +} #endif
#endif /*__S3C6400_H__*/ diff --git a/board/samsung/smdk6400/Makefile b/board/samsung/smdk6400/Makefile index f7fa667..e21a8c1 100644 --- a/board/samsung/smdk6400/Makefile +++ b/board/samsung/smdk6400/Makefile @@ -31,8 +31,9 @@ LIB = $(obj)lib$(BOARD).o ifndef CONFIG_SPL_BUILD COBJS-y := smdk6400.o endif +COBJS-y += dmc_init.o
-SOBJS := lowlevel_init.o mem_init.o +SOBJS := lowlevel_init.o
ifdef CONFIG_SPL_BUILD COBJS-y += smdk6400_nand_spl.o diff --git a/board/samsung/smdk6400/dmc_init.c b/board/samsung/smdk6400/dmc_init.c new file mode 100644 index 0000000..776536c --- /dev/null +++ b/board/samsung/smdk6400/dmc_init.c @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2012 + * Zhong Hongbo bocui107@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/io.h> +#include <asm/arch/dmc.h> +#include <asm/arch/s3c6400.h> +#include "setup.h" + +void memory_timing_parameter(struct s3c64xx_dmc *dmc) +{ + + writel(DMC_DDR_REFRESH_PRD, &dmc->refresh); + + writel(DMC_DDR_CAS_LATENCY, &dmc->caslat); + + writel(DMC_DDR_t_DQSS, &dmc->t_dqss); + + writel(DMC_DDR_t_MRD, &dmc->t_mrd); + + writel(DMC_DDR_t_RAS, &dmc->t_ras); + + writel(DMC_DDR_t_RC, &dmc->t_rc); + + writel((DMC_DDR_t_RFC | DMC_DDR_schedule_RFC), &dmc->t_rfc); + + writel((DMC_DDR_t_RP | DMC_DDR_schedule_RP), &dmc->t_rp); + + writel(DMC_DDR_t_RRD, &dmc->t_rrd); + + writel(DMC_DDR_t_WR, &dmc->t_wr); + + writel(DMC_DDR_t_WTR, &dmc->t_wtr); + + writel(DMC_DDR_t_XP, &dmc->t_xp); + + writel(DMC_DDR_t_XSR, &dmc->t_xsr); + + writel(DMC_DDR_t_ESR, &dmc->t_esr); +} + +void memory_init_sequence(struct s3c64xx_dmc *dmc) +{ + /* DMC0 DDR Chip 0 configuration direct command reg */ + writel(DMC_NOP0, &dmc->directcmd); + + /* Precharge All */ + writel(DMC_PA0, &dmc->directcmd); + + /* Auto Refresh 2 time */ + writel(DMC_AR0, &dmc->directcmd); + writel(DMC_AR0, &dmc->directcmd); + + /* MRS */ + writel(DMC_mDDR_EMR0, &dmc->directcmd); + + /* Mode Reg */ + writel(DMC_mDDR_MR0, &dmc->directcmd); +} + +void mem_ctrl_init(void) +{ + struct s3c64xx_dmc *dmc = (struct s3c64xx_dmc *)s3c64xx_get_base_dmc1(); + unsigned long val; + + /* Change the DRAM controller to 'Config' state */ + val = readl(&dmc->memcmd); + val &= ~0x7; + val |= 0x4; + writel(val, &dmc->memcmd); + + memory_timing_parameter(dmc); + + writel(DMC1_MEM_CFG, &dmc->memcfg); + writel(DMC1_MEM_CFG2, &dmc->memcfg2); + + writel(DMC1_CHIP0_CFG, &dmc->chip_0_cfg); + writel(DMC_DDR_32_CFG, &dmc->user_config); + + memory_init_sequence(dmc); + + /* Enable DMC1 */ + writel(0x0, &dmc->memcmd); + + /* Check memory statute: 0x1 means 'Ready' */ + do { + val = readl(&dmc->memstat); + val &= 0x3; + } while (val != 0x1); +} diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S index 57989bc..e142217 100644 --- a/board/samsung/smdk6400/lowlevel_init.S +++ b/board/samsung/smdk6400/lowlevel_init.S @@ -103,7 +103,7 @@ lowlevel_init: mov r1, #S3C64XX_MEM_SYS_CFG_NAND str r1, [r0]
- bl mem_ctrl_asm_init + bl mem_ctrl_init #endif
#ifndef CONFIG_SPL_BUILD diff --git a/board/samsung/smdk6400/mem_init.S b/board/samsung/smdk6400/mem_init.S deleted file mode 100644 index df88cba..0000000 --- a/board/samsung/smdk6400/mem_init.S +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400 - * - * Copyright (C) 2008 - * Guennadi Liakhovetki, DENX Software Engineering, lg@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/arch/s3c6400.h> - - .globl mem_ctrl_asm_init -mem_ctrl_asm_init: - /* DMC1 base address 0x7e001000 */ - ldr r0, =ELFIN_DMC1_BASE - - ldr r1, =0x4 - str r1, [r0, #INDEX_DMC_MEMC_CMD] - - ldr r1, =DMC_DDR_REFRESH_PRD - str r1, [r0, #INDEX_DMC_REFRESH_PRD] - - ldr r1, =DMC_DDR_CAS_LATENCY - str r1, [r0, #INDEX_DMC_CAS_LATENCY] - - ldr r1, =DMC_DDR_t_DQSS - str r1, [r0, #INDEX_DMC_T_DQSS] - - ldr r1, =DMC_DDR_t_MRD - str r1, [r0, #INDEX_DMC_T_MRD] - - ldr r1, =DMC_DDR_t_RAS - str r1, [r0, #INDEX_DMC_T_RAS] - - ldr r1, =DMC_DDR_t_RC - str r1, [r0, #INDEX_DMC_T_RC] - - ldr r1, =DMC_DDR_t_RCD - ldr r2, =DMC_DDR_schedule_RCD - orr r1, r1, r2 - str r1, [r0, #INDEX_DMC_T_RCD] - - ldr r1, =DMC_DDR_t_RFC - ldr r2, =DMC_DDR_schedule_RFC - orr r1, r1, r2 - str r1, [r0, #INDEX_DMC_T_RFC] - - ldr r1, =DMC_DDR_t_RP - ldr r2, =DMC_DDR_schedule_RP - orr r1, r1, r2 - str r1, [r0, #INDEX_DMC_T_RP] - - ldr r1, =DMC_DDR_t_RRD - str r1, [r0, #INDEX_DMC_T_RRD] - - ldr r1, =DMC_DDR_t_WR - str r1, [r0, #INDEX_DMC_T_WR] - - ldr r1, =DMC_DDR_t_WTR - str r1, [r0, #INDEX_DMC_T_WTR] - - ldr r1, =DMC_DDR_t_XP - str r1, [r0, #INDEX_DMC_T_XP] - - ldr r1, =DMC_DDR_t_XSR - str r1, [r0, #INDEX_DMC_T_XSR] - - ldr r1, =DMC_DDR_t_ESR - str r1, [r0, #INDEX_DMC_T_ESR] - - ldr r1, =DMC1_MEM_CFG - str r1, [r0, #INDEX_DMC_MEMORY_CFG] - - ldr r1, =DMC1_MEM_CFG2 - str r1, [r0, #INDEX_DMC_MEMORY_CFG2] - - ldr r1, =DMC1_CHIP0_CFG - str r1, [r0, #INDEX_DMC_CHIP_0_CFG] - - ldr r1, =DMC_DDR_32_CFG - str r1, [r0, #INDEX_DMC_USER_CONFIG] - - /* DMC0 DDR Chip 0 configuration direct command reg */ - ldr r1, =DMC_NOP0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Precharge All */ - ldr r1, =DMC_PA0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Auto Refresh 2 time */ - ldr r1, =DMC_AR0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* MRS */ - ldr r1, =DMC_mDDR_EMR0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Mode Reg */ - ldr r1, =DMC_mDDR_MR0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Enable DMC1 */ - mov r1, #0x0 - str r1, [r0, #INDEX_DMC_MEMC_CMD] - -check_dmc1_ready: - ldr r1, [r0, #INDEX_DMC_MEMC_STATUS] - mov r2, #0x3 - and r1, r1, r2 - cmp r1, #0x1 - bne check_dmc1_ready - nop - - mov pc, lr - - .ltorg diff --git a/board/samsung/smdk6400/setup.h b/board/samsung/smdk6400/setup.h index 5e97b27..63a4a8d 100644 --- a/board/samsung/smdk6400/setup.h +++ b/board/samsung/smdk6400/setup.h @@ -49,4 +49,89 @@
#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ (STARTUP_HCLKDIV + 1)) + +#define S3C64XX_MEM_SYS_CFG_NAND 0x0008 + +/* + * Memory Chip direct command + */ +#define DMC_NOP0 0x0c0000 +#define DMC_NOP1 0x1c0000 +#define DMC_PA0 0x000000 /* Precharge all */ +#define DMC_PA1 0x100000 +#define DMC_AR0 0x040000 /* Autorefresh */ +#define DMC_AR1 0x140000 +#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */ +#define DMC_SDR_MR1 0x180032 +#define DMC_DDR_MR0 0x080162 +#define DMC_DDR_MR1 0x180162 +#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */ +#define DMC_mDDR_MR1 0x180032 +#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */ +#define DMC_mSDR_EMR1 0x1a0000 +#define DMC_DDR_EMR0 0x090000 +#define DMC_DDR_EMR1 0x190000 +#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */ +#define DMC_mDDR_EMR1 0x1a0000 + +/* + * Physical Memory Map + */ +#define DMC1_MEM_CFG 0x00010012 /* burst 4, 13-bit row, 10-bit col */ +#define DMC1_MEM_CFG2 0xB45 +#define DMC1_CHIP0_CFG 0x150F8 /* 0x5000_0000~0x57ff_ffff (128 MiB) */ +#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */ + +/* Memory Parameters */ +/* DDR Parameters */ +#define DDR_tREFRESH 7800 /* ns */ +#define DDR_tRAS 45 /* ns (min: 45ns)*/ +#define DDR_tRC 68 /* ns (min: 67.5ns)*/ +#define DDR_tRCD 23 /* ns (min: 22.5ns)*/ +#define DDR_tRFC 80 /* ns (min: 80ns)*/ +#define DDR_tRP 23 /* ns (min: 22.5ns)*/ +#define DDR_tRRD 15 /* ns (min: 15ns)*/ +#define DDR_tWR 15 /* ns (min: 15ns)*/ +#define DDR_tXSR 120 /* ns (min: 120ns)*/ +#define DDR_CASL 3 /* CAS Latency 3 */ + +/* + * mDDR memory configuration + */ +#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000) + +#define DMC_DDR_BA_EMRS 2 +#define DMC_DDR_MEM_CASLAT 3 +#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1) +#define DMC_DDR_t_DQSS 1 +#define DMC_DDR_t_MRD 2 +#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1) +#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1) +#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1) +#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3) +#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1) +#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5) +#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1) +#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3) +#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1) +#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1) +#define DMC_DDR_t_WTR 2 +#define DMC_DDR_t_DQSS 1 +#define DMC_DDR_t_MRD 2 +#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1) +#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1) +#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1) +#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3) +#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1) +#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5) +#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1) +#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3) +#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1) +#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1) +#define DMC_DDR_t_WTR 2 +#define DMC_DDR_t_XP 2 +#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1) +#define DMC_DDR_t_ESR DMC_DDR_t_XSR +#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH)) +#define DMC_DDR_USER_CONFIG 1 #endif