A special configuration is needed to build U-Boot, SPL and the FlexSPI Configuration block. Add a defconfig with this added and enable SPI booting from the board file.
Signed-off-by: Adam Ford aford173@gmail.com
diff --git a/board/beacon/imx8mm/MAINTAINERS b/board/beacon/imx8mm/MAINTAINERS index e887db20a2..d28ebdad96 100644 --- a/board/beacon/imx8mm/MAINTAINERS +++ b/board/beacon/imx8mm/MAINTAINERS @@ -5,3 +5,10 @@ S: Maintained F: board/beacon/imx8mm/ F: include/configs/imx8mm_beacon.h F: configs/imx8mm_beacon_defconfig +F: configs/imx8mm_beacon_fspi_defconfig +F: arch/arm/dts/imx8mm-beacon-baseboard.dtsi +F: arch/arm/dts/imx8mm-beacon-kit.dts +F: arch/arm/dts/imx8mm-beacon-kit-flexspi.dtb +F: arch/arm/dts/imx8mm-beacon-kit-flexspi.dts +F: arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi +F: arch/arm/dts/imx8mm-beacon-som.dtsi diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c index 12266b22a4..a1485ee944 100644 --- a/board/beacon/imx8mm/spl.c +++ b/board/beacon/imx8mm/spl.c @@ -34,6 +34,10 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) case SD3_BOOT: case MMC3_BOOT: return BOOT_DEVICE_MMC2; + case QSPI_BOOT: + return BOOT_DEVICE_SPI; + case USB_BOOT: + return BOOT_DEVICE_BOARD; default: return BOOT_DEVICE_NONE; } diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig new file mode 100644 index 0000000000..f41fbe6273 --- /dev/null +++ b/configs/imx8mm_beacon_fspi_defconfig @@ -0,0 +1,129 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx8m/imximage-8mm-flexspi-lpddr4.cfg" +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-beacon-kit-flexspi" +CONFIG_SPL_TEXT_BASE=0x7E2000 +CONFIG_TARGET_IMX8MM_BEACON=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_LTO=y +CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi;" +CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit-flexspi.dtb" +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_POWER=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x600000 +CONFIG_SPL_WATCHDOG=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MM=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=10000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_BD71837=y +CONFIG_SPL_DM_REGULATOR_BD71837=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_CONS_INDEX=2 +CONFIG_DM_SERIAL=y +# CONFIG_SPL_DM_SERIAL is not set +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_WATCHDOG=y