6 Jul
2021
6 Jul
'21
2:21 p.m.
On Wed, Jun 30, 2021 at 11:23:50PM +0800, Zong Li wrote:
There are two revisions of unmatched board with different DDR timing, we'd like to support multi-dtb mechanism in SPL, then it selects the right DTB at runtime according to PCB revision in I2C EEPROM.
Signed-off-by: Zong Li zong.li@sifive.com
board/sifive/unmatched/spl.c | 28 ++++++++++++++++++++++++++-- configs/sifive_unmatched_defconfig | 4 ++++ 2 files changed, 30 insertions(+), 2 deletions(-)
Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com