The NXP i.MXRT1170 Evaluation Kit (EVK) provides a platform for rapid evaluation of the i.MXRT, which features NXP's implementation of the Arm Cortex-M7 and Cortex-M4 core.
The EVK provides 64 MB SDRAM, Micro SD card socket, USB 2.0 OTG.
This patch aims to support the preliminary booting up features as follows: GPIO LPUART SD/MMC SDRAM
Signed-off-by: Jesse Taube Mr.Bossman075@gmail.com --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imxrt1170-evk-u-boot.dtsi | 106 ++++++++++ arch/arm/dts/imxrt1170-evk.dts | 246 ++++++++++++++++++++++ arch/arm/dts/imxrt1170.dtsi | 274 +++++++++++++++++++++++++ 4 files changed, 628 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imxrt1170-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imxrt1170-evk.dts create mode 100644 arch/arm/dts/imxrt1170.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cc34da7bd8..cf5f668b62 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -910,7 +910,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-pico-pi.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ - imxrt1020-evk.dtb + imxrt1020-evk.dtb \ + imxrt1170-evk.dtb \
dtb-$(CONFIG_RCAR_GEN2) += \ r8a7790-lager-u-boot.dtb \ diff --git a/arch/arm/dts/imxrt1170-evk-u-boot.dtsi b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi new file mode 100644 index 0000000000..ebc3a5051c --- /dev/null +++ b/arch/arm/dts/imxrt1170-evk-u-boot.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube Mr.Bossman075@gmail.com + * Giulio Benetti giulio.benetti@benettiengineering.com + */ + +/ { + chosen { + u-boot,dm-spl; + }; + + clocks { + u-boot,dm-spl; + }; + + soc { + u-boot,dm-spl; + }; +}; + +&osc { + u-boot,dm-spl; +}; + +&osc32k { + u-boot,dm-spl; +}; + +&rcosc48M_div2 { + u-boot,dm-spl; +}; + +&rcosc48M { + u-boot,dm-spl; +}; + +&rcosc400M { + u-boot,dm-spl; +}; + +&rcosc16M { + u-boot,dm-spl; +}; + +&clks { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&gpt1 { + u-boot,dm-spl; +}; + +&lpuart1 { /* console */ + u-boot,dm-spl; +}; + +&semc { + u-boot,dm-spl; + + bank1: bank@0 { + u-boot,dm-spl; + }; +}; + +&iomuxc { + u-boot,dm-spl; + + imxrt1170-evk { + u-boot,dm-spl; + pinctrl_lpuart1: lpuart1grp { + u-boot,dm-spl; + }; + + pinctrl_usdhc0: usdhc0grp { + u-boot,dm-spl; + }; + pinctrl_semc: semcgrp { + u-boot,dm-spl; + }; + }; +}; + +&usdhc1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imxrt1170-evk.dts b/arch/arm/dts/imxrt1170-evk.dts new file mode 100644 index 0000000000..e612eda5ca --- /dev/null +++ b/arch/arm/dts/imxrt1170-evk.dts @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube Mr.Bossman075@gmail.com + * Giulio Benetti giulio.benetti@benettiengineering.com + */ + +/dts-v1/; +#include "imxrt1170.dtsi" +#include "imxrt1170-evk-u-boot.dtsi" +#include "imxrt1170-pinfunc.h" + +/ { + model = "NXP imxrt1170-evk board"; + compatible = "fsl,imxrt1170-evk", "fsl,imxrt1170"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + tick-timer = &gpt1; + }; + + memory@20240000 { + device_type = "memory"; + reg = <0x20240000 0xf0000>; + }; + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x4000000>; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&semc { + /* + * Memory configuration from sdram datasheet IS42S16160J-6BLI + */ + fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8 + 0 + 0 + 0 + 0 + 0>; + fsl,sdram-control = /bits/ 8 <MEM_WIDTH_32BITS + BL_8 + COL_9BITS + CL_3>; + fsl,sdram-timing = /bits/ 8 <0x2 + 0x2 + 0xd + 0x0 + 0x8 + 0x7 + + 0x0d + 0x0b + 0x00 + 0x00 + + 0x00 + 0x0A + 0x08 + 0x09>; + + bank1: bank@0 { + fsl,base-address = <0x80000000>; + fsl,memory-size = <MEM_SIZE_64M>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + + imxrt1170-evk { + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IOMUXC_GPIO_AD_24_LPUART1_TXD 0xf1 + IOMUXC_GPIO_AD_25_LPUART1_RXD 0xf1 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + IOMUXC_GPIO_AD_32_USDHC1_CD_B + 0x1B000 + IOMUXC_GPIO_AD_34_USDHC1_VSELECT + 0xB069 + IOMUXC_GPIO_SD_B1_00_USDHC1_CMD + 0x17061 + IOMUXC_GPIO_SD_B1_01_USDHC1_CLK + 0x17061 + IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 + 0x17061 + IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 + 0x17061 + IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 + 0x17061 + IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 + 0x17061 + >; + }; + pinctrl_semc: semcgrp { + fsl,pins = < + IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 + 8 /* SEMC_D0 */ + IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 + 8 /* SEMC_D1 */ + IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 + 8 /* SEMC_D2 */ + IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 + 8 /* SEMC_D3 */ + IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 + 8 /* SEMC_D4 */ + IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 + 8 /* SEMC_D5 */ + IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 + 8 /* SEMC_D6 */ + IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 + 8 /* SEMC_D7 */ + IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 + 8 /* SEMC_DM0 */ + IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 + 8 /* SEMC_A0 */ + IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 + 8 /* SEMC_A1 */ + IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 + 8 /* SEMC_A2 */ + IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 + 8 /* SEMC_A3 */ + IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 + 8 /* SEMC_A4 */ + IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 + 8 /* SEMC_A5 */ + IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 + 8 /* SEMC_A6 */ + IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 + 8 /* SEMC_A7 */ + IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 + 8 /* SEMC_A8 */ + IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 + 8 /* SEMC_A9 */ + IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 + 8 /* SEMC_A11 */ + IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 + 8 /* SEMC_A12 */ + IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 + 8 /* SEMC_BA0 */ + IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 + 8 /* SEMC_BA1 */ + IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 + 8 /* SEMC_A10 */ + IOMUXC_GPIO_EMC_B1_24_SEMC_CAS + 8 /* SEMC_CAS */ + IOMUXC_GPIO_EMC_B1_25_SEMC_RAS + 8 /* SEMC_RAS */ + IOMUXC_GPIO_EMC_B1_26_SEMC_CLK + 8 /* SEMC_CLK */ + IOMUXC_GPIO_EMC_B1_27_SEMC_CKE + 8 /* SEMC_CKE */ + IOMUXC_GPIO_EMC_B1_28_SEMC_WE + 8 /* SEMC_WE */ + IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 + 8 /* SEMC_CS0 */ + IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 + 8 /* SEMC_D8 */ + IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 + 8 /* SEMC_D9 */ + IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 + 8 /* SEMC_D10 */ + IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 + 8 /* SEMC_D11 */ + IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 + 8 /* SEMC_D12 */ + IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 + 8 /* SEMC_D13 */ + IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 + 8 /* SEMC_D14 */ + IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 + 8 /* SEMC_D15 */ + IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 + 8 /* SEMC_DM00 */ + IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 + 8 /* SEMC_DM01 */ + IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 + 4 /* SEMC_DM02 */ + IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 + 8 /* SEMC_DM03 */ + IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 + 8 /* SEMC_D16 */ + IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 + 8 /* SEMC_D17 */ + IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 + 8 /* SEMC_D18 */ + IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 + 8 /* SEMC_D19 */ + IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 + 8 /* SEMC_D20 */ + IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 + 8 /* SEMC_D21 */ + IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 + 8 /* SEMC_D22 */ + IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 + 8 /* SEMC_D23 */ + IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 + 8 /* SEMC_D24 */ + IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 + 8 /* SEMC_D25 */ + IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 + 4 /* SEMC_D26 */ + IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 + 8 /* SEMC_D27 */ + IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 + 8 /* SEMC_D28 */ + IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 + 8 /* SEMC_D29 */ + IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 + 8 /* SEMC_D30 */ + IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 + 8 /* SEMC_D31 */ + IOMUXC_GPIO_EMC_B1_39_SEMC_DQS + (IMX_PAD_SION | 8) /* SEMC_DQS */ + >; + }; + }; +}; + +&gpt1 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; + status = "okay"; + broken-cd; + //cd-gpios = <&gpio8 31 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/imxrt1170.dtsi b/arch/arm/dts/imxrt1170.dtsi new file mode 100644 index 0000000000..88024f1f90 --- /dev/null +++ b/arch/arm/dts/imxrt1170.dtsi @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube Mr.Bossman075@gmail.com + * Giulio Benetti giulio.benetti@benettiengineering.com + */ + +#include "armv7-m.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/imxrt1170-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/memory/imxrt-sdram.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; + gpio7 = &gpio8; + gpio8 = &gpio9; + gpio9 = &gpio10; + gpio10 = &gpio11; + gpio11 = &gpio12; + gpio12 = &gpio13; + mmc0 = &usdhc1; + serial0 = &lpuart1; + }; + + clocks { + osc: osc { + compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + osc32k: osc32k { + compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + rcosc48M_div2: rcosc48M_div2 { + compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + rcosc48M: rcosc48M { + compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + rcosc400M: rcosc400M { + compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + + rcosc16M: rcosc16M { + compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + }; + + soc { + semc: semc@400d4000 { + compatible = "fsl,imxrt-semc"; + reg = <0x400d4000 0x4000>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMXRT1170_CLK_SEMC>; + pinctrl-0 = <&pinctrl_semc>; + pinctrl-names = "default"; + status = "okay"; + }; + + lpuart1: serial@4007c000 { + compatible = "fsl,imxrt-lpuart"; + reg = <0x4007c000 0x4000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMXRT1170_CLK_LPUART1>; + clock-names = "per"; + status = "disabled"; + }; + + iomuxc: iomuxc@400e8000 { + compatible = "fsl,imxrt-iomuxc"; + reg = <0x400e8000 0x4000>; + fsl,mux_mask = <0x7>; + }; + + anatop: anatop@40c84000 { + compatible = "fsl,imxrt-anatop"; + reg = <0x40c84000 0x4000>; + }; + + clks: ccm@40cc0000 { + compatible = "fsl,imxrt1170-ccm"; + reg = <0x40cc0000 0x4000>; + #clock-cells = <1>; + }; + + usdhc1: usdhc@40418000 { + compatible = "fsl,imxrt-usdhc"; + reg = <0x40418000 0x10000>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMXRT1170_CLK_USDHC1>; + clock-names = "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + gpio1: gpio@4012c000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x4012c000 0x4000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@40130000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40130000 0x4000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@40134000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40134000 0x4000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@40138000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40138000 0x4000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@4013c000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x4013c000 0x4000>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@40140000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40140000 0x4000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@40c5c000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40c5c000 0x4000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio8: gpio@40c60000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40c60000 0x4000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio9: gpio@40c64000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40c64000 0x4000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio10: gpio@40c68000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40c68000 0x4000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio11: gpio@40c6c000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40c6c000 0x4000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio12: gpio@40c70000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40c70000 0x4000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; // only cm4 + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio13: gpio@40ca0000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x40ca0000 0x4000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpt1: gpt1@400ec000 { + compatible = "fsl,imxrt-gpt"; + reg = <0x400ec000 0x4000>; + interrupts = <119>; + clocks = <&clks IMXRT1170_CLK_GPT1>; + status = "disabled"; + }; + }; +};