-----Original Message----- From: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Sent: Wednesday, March 24, 2021 2:20 PM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Tan, Ley Foon ley.foon.tan@intel.com; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org; Gan, Yau Wai yau.wai.gan@intel.com; Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Subject: [v2 2/2] arm: socfpga: Changed to store QSPI reference clock in kHz
Changed to store QSPI reference clock in kHz instead of Hz in boot scratch cold0 register for Stratix10 and Agilex.
This patch is in preparation for Intel N5X SDRAM driver support. Reserved 4 bits for Intel N5X SDRAM driver, and there will be 28 bits to store QSPI reference clock. Due to limited bits, QSPI reference clock frequency is converted to kHz from Hz.
Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
v2:
- Rename mbox_qspi_set_controller_clk_hz function to cm_set_qspi_controller_clk_hz function and move to clock_manager.c.
- Remove CLOCK_1K macro from socfpga_soc64_common.h
- Sort include file list by alphabetical order in mailbox_s10.c
Reviewed-by: Ley Foon Tan ley.foon.tan@intel.com