12 Mar
2024
12 Mar
'24
4:11 p.m.
On 3/7/24 16:29, lukas.funke-oss@weidmueller.com wrote:
From: Lukas Funke lukas.funke@weidmueller.com
ZynqMP CG series devices only have two cpus. In this case the interrupt-affinity property has to adapted, because cpu3 and cpu4 are missing. By adding a label to the pmu fwnode the interrupt-affinity can be adapted in a device specific DT.
Signed-off-by: Lukas Funke lukas.funke@weidmueller.com
arch/arm/dts/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index b50b83b772..457f8e394f 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -168,7 +168,7 @@ bootph-all; };
- pmu {
- pmu: pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
Applied. M