Stephen,
-----Original Message----- From: Stephen Warren [mailto:swarren@wwwdotorg.org] Sent: Tuesday, March 12, 2013 10:41 AM To: Tom Warren Cc: u-boot@lists.denx.de; Stephen Warren; Tom Warren Subject: Re: [U-Boot] [PATCH] Tegra114: Dalmore: Add pad config tables/code based on pinmux code
On 03/12/2013 10:09 AM, Tom Warren wrote:
Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init().
Currently, no padcfg entries exist. SDIO3CFG will be added when the MMC driver is added as per the TRM to work with the SD-card slot on Dalmore E1611.
Much of the pinmux driver code here is common with Tegra30. We should at least file a bug to move it to a common file at some point.
I'd planned on sending a patchset after this was reviewed/accepted, but I'll file a bug as a reminder.
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h
+#define PGRP_SLWF_NONE -1 +#define PGRP_SLWF_MAX 3 +#define PGRP_SLWR_NONE PGRP_SLWF_NONE +#define PGRP_SLWR_MAX PGRP_SLWF_MAX
+#define PGRP_DRVUP_NONE -1 +#define PGRP_DRVUP_MAX 127 +#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE +#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
There seems to be some mixed use of TABs/spaces there. Feel free to fix up when you apply it.
Will do. Thanks.
Aside from that, Reviewed-by: Stephen Warren swarren@nvidia.com
-- nvpublic