CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT is not the correct method to set I/O to 1.8. To boards that does not support vqmmc-supply, use vs18_enable in fsl_esdhc_cfg. If regulator is supported, use fixed 1.8V regulator for vqmmc-supply.
Signed-off-by: Peng Fan peng.fan@nxp.com Cc: Jaehoon Chung jh80.chung@samsung.com Cc: York Sun york.sun@nxp.com Cc: Stefano Babic sbabic@denx.de --- doc/README.fsl-esdhc | 2 -- drivers/mmc/fsl_esdhc.c | 4 ---- scripts/config_whitelist.txt | 1 - 3 files changed, 7 deletions(-)
diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc index 7e71387..29cc661 100644 --- a/doc/README.fsl-esdhc +++ b/doc/README.fsl-esdhc @@ -20,5 +20,3 @@ Freescale esdhc-specific options - CONFIG_SYS_FSL_ESDHC_BE ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined by ESDHC IP's endian mode or processor's endian mode. - - - CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V. diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 9ebde32..4819bab 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -671,10 +671,6 @@ static int esdhc_init(struct mmc *mmc) /* Set timout to the maximum value */ esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
-#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT - esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); -#endif - if (priv->vs18_enable) esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index d487be7..c51bb2f 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3961,7 +3961,6 @@ CONFIG_SYS_FSL_ERRATUM_A_004934 CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_FSL_ESDHC_BE CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE CONFIG_SYS_FSL_ESDHC_LE CONFIG_SYS_FSL_ESDHC_NUM