On 02/08/12 11:30, Stefano Babic wrote:
From: Ilya Yanok yanok@emcraft.com
This patch adds support for the HTKW mcx AM3517-based board. Serial, Ethernet, NAND, MMC, RTC, EHCI USB host and both NAND and MMC SPLs are supported.
Signed-off-by: Ilya Yanok yanok@emcraft.com Signed-off-by: Stefano Babic sbabic@denx.de CC: Tom Rini tom.rini@gmail.com Cc: Detlev Zundel dzu@denx.de
Acked-by: Igor Grinberg grinberg@compulab.co.il
Changes since V7:
- do not use temporary variable to return values (Igor Grinberg)
- port 2 is TTL, cannot be PHY (Igor Grinberg)
Changes from V6:
- rebased on current u-boot-ti
- applied and tested on top of EHCI Gavindraj's patches
- uses ULPI framework
Changes from V5 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/120254
- added comments on CONFIG_SYS_TEXT_BASE and SPL_{MALLOC,BSS}
Changes from V4 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/120148
- board_mmc_init return value fixed
- machine id added locally
- CONFIG_SYS_NAND_U_BOOT_SIZE removed
Changes from V3 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/118530
- Comment for misc_init_r function fixed
- Added check for gpio_request return value.
- Removed #if defined(CONFIG_GENERIC_MMC) around board_mmc_init
- CONFIG_USE_IRQ and related stuff removed from config
- CONFIG_OMAP3_MICRON_DDR removed
- CONFIG_SYS_MAXRAGS changed 32 -> 16
- Incorrect multiline comments (/*--- ones) fixed
- CONFIG_SPL_MAX_SIZE rewritten 0xB400 -> (45 << 10)
- CONFIG_SPL_NAND_WORKSPACE removed
Changes from V2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/116548
- None
Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/115026
- Calls to gpio_set_value after gpio_direction_output removed
- Minor style problem (tab instead of space) fixed
SPL series: Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112892
- OMAP EHCI support enabled in config
- MMC SPL support enabled in config
"DaVinci EMAC and HTKW mcx support" series: Changes from V3 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112884
- NAND SPL support enabled in config
Changes from V2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112317
- removed dead code from board/htkw/mcx/Makefile as Mike suggested
- removed EMAC reset (now done in generic cpu_eth_init())
- removed some unsuned defines from configuration header
Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/111197
- various style fixes to make checkpatch (almost) happy
- FSF address removed from GPL comments
- CONFIG_SYS_TEXT_BASE moved to configuration header, config.mk droped
- CONFIG_MACH_TYPE is used instead of setting mach type from board code
- i2c_init removed from misc_init_r
- cpu_eth_init removed (added to generic place by another patch)
- CONTROL_PADCONF defines removed
- Fixed boolean config options not to have a value
- CONFIG_MUSB_* and related defines removed
MAINTAINERS | 4 + board/htkw/mcx/Makefile | 38 +++++ board/htkw/mcx/mcx.c | 112 +++++++++++++ board/htkw/mcx/mcx.h | 408 +++++++++++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/mcx.h | 378 +++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 941 insertions(+), 0 deletions(-) create mode 100644 board/htkw/mcx/Makefile create mode 100644 board/htkw/mcx/mcx.c create mode 100644 board/htkw/mcx/mcx.h create mode 100644 include/configs/mcx.h
diff --git a/MAINTAINERS b/MAINTAINERS index a8e56bb..7e52f50 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -920,6 +920,10 @@ Richard Woodruff r-woodruff2@ti.com
omap2420h4 ARM1136EJS
+Ilya Yanok yanok@emcraft.com
- mcx ARM ARMV7 (AM35x SoC)
Syed Mohammed Khasim sm.khasim@gmail.com Sughosh Ganu urwithsughosh@gmail.com
diff --git a/board/htkw/mcx/Makefile b/board/htkw/mcx/Makefile new file mode 100644 index 0000000..4c8db10 --- /dev/null +++ b/board/htkw/mcx/Makefile @@ -0,0 +1,38 @@ +# +# Copyright (C) 2011 Ilya Yanok, Emcraft Systems +# +# Based on ti/evm/Makefile +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +#
+include $(TOPDIR)/config.mk
+LIB = $(obj)lib$(BOARD).o
+COBJS := $(BOARD).o
+SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS))
+$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
+#########################################################################
+# defines $(obj).depend target +include $(SRCTREE)/rules.mk
+sinclude $(obj).depend diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c new file mode 100644 index 0000000..e593b43 --- /dev/null +++ b/board/htkw/mcx/mcx.c @@ -0,0 +1,112 @@ +/*
- Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- Based on ti/evm/evm.c
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc.
- */
+#include <common.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include <asm/gpio.h> +#include <asm/omap_gpio.h> +#include "errno.h" +#include <i2c.h> +#ifdef CONFIG_USB_EHCI +#include <usb.h> +#include <asm/ehci-omap.h> +#endif +#include "mcx.h"
+DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_USB_EHCI +static struct omap_usbhs_board_data usbhs_bdata = {
- .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+int ehci_hcd_init(void) +{
- return omap_ehci_hcd_init(&usbhs_bdata);
+}
+int ehci_hcd_stop(void) +{
- return omap_ehci_hcd_stop();
+} +#endif
+/*
- Routine: board_init
- Description: Early hardware init.
- */
+int board_init(void) +{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
- return 0;
+}
+/*
- Routine: misc_init_r
- Description: late init.
- */
+int misc_init_r(void) +{
- dieid_num_r();
- return 0;
+}
+/*
- Routine: set_muxconf_regs
- Description: Setting up the configuration Mux registers specific to the
hardware. Many pins need to be moved from protect to primary
mode.- */
+void set_muxconf_regs(void) +{
- MUX_MCX();
+}
+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{
- return omap_mmc_init(0);
+} +#endif
+#ifdef CONFIG_USB_EHCI_OMAP +#define USB_HOST_PWR_EN 132 +int board_usb_init(void) +{
- if (gpio_request(USB_HOST_PWR_EN, "USB_HOST_PWR_EN") < 0) {
puts("Failed to get USB_HOST_PWR_EN pin\n");return -ENODEV;- }
- gpio_direction_output(USB_HOST_PWR_EN, 1);
- return 0;
+} +#endif diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h new file mode 100644 index 0000000..d675a48 --- /dev/null +++ b/board/htkw/mcx/mcx.h @@ -0,0 +1,408 @@ +/*
- Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- Based on ti/evm/evm.h
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc.
- */
+#ifndef _AM3517EVM_H_ +#define _AM3517EVM_H_
+const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "HTKW mcx Board",
- "NAND",
+};
+/*
- IEN - Input Enable
- IDIS - Input Disable
- PTD - Pull type Down
- PTU - Pull type Up
- DIS - Pull type selection is inactive
- EN - Pull type selection is active
- M0 - Mode 0
- The commented string gives the final mux configuration for that pin
- */
+#define MUX_MCX() \
- /* SDRC */\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_CKE0), (M0)) \
- MUX_VAL(CP(SDRC_CKE1), (M0)) \
- MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
/*sdrc_strben_dly0*/\- MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
/*sdrc_strben_dly1*/\- /* GPMC */\
- MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | DIS | M4)) \
/* GPIO_43 LCD buffer enable */ \- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) \
/* GPIO_57 TS_PenIRQn */\- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) \
/* GPIO_58 ETHERNET RESET */\- MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | DIS | M4)) \
/* GPIO_61 SD-CARD CD */ \- MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \
/* GPIO_62 Nand write protect, keep enabled */ \- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
/* GPIO_65 SD-CARD WP */\- /* DSS */\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA0), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(DSS_DATA1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA8), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA9), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA16), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA17), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA18), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
- /* CAMERA */\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) \
- /* MMC */\
- MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
- \
- MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(MMC2_CMD), (IDIS | PTD | DIS | M4)) \
/* GPIO_131 LCD Enable */ \- MUX_VAL(CP(MMC2_DAT0), (IDIS | PTD | DIS | M4)) \
/* GPIO_132 USB host Enable */\- MUX_VAL(CP(MMC2_DAT1), (IDIS | PTD | DIS | M4)) \
/* GPIO_133 HDMI PD */\- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4))\
- /* McBSP */\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP2_DX), (IEN | PTU | EN | M4))\
- \
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4))\
- \
- MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) \
/* GPIO_152 USB phy2 reset */\- MUX_VAL(CP(MCBSP4_DR), (IEN | PTU | EN | M4)) \
/* GPIO_153 */\- MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) \
/* GPIO_154 USB phy1 reset */\- MUX_VAL(CP(MCBSP4_FSX), (IEN | PTU | EN | M4)) \
/* GPIO_155 TS_BUSY */\- /* UART */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
- /* I2C */\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
- /* McSPI */\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat7 */\- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat4 */\- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat5 */\- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat6 */\- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat3 */\- /* CCDC */\
- MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_HD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | EN | M4)) \
- /* RMII */\
- MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
- MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
- MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
- MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
- /* HECC */\
- MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M4)) \
- /* HSUSB */\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
- /* HDQ */\
- MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
- /* Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | DIS | M4)) \
/* SYS_nRESWARM */\- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))\
- MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4))\
- MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | DIS | M4)) \
- \
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\
- MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\
- /* JTAG */\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | EN | M4))\
- /* ETK (ES2 onwards) */\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
/* hsusb1_stp */ \- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
/* hsusb1_clk */\- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
- /* Die to Die */\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
+#endif diff --git a/boards.cfg b/boards.cfg index 1f264b1..70809ca 100644 --- a/boards.cfg +++ b/boards.cfg @@ -214,6 +214,7 @@ omap3_evm_quick_mmc arm armv7 evm ti omap3_evm_quick_nand arm armv7 evm ti omap3 omap3_sdp3430 arm armv7 sdp3430 ti omap3 devkit8000 arm armv7 devkit8000 timll omap3 +mcx arm armv7 mcx htkw omap3 tricorder arm armv7 tricorder corscience omap3 twister arm armv7 twister technexion omap3 omap4_panda arm armv7 panda ti omap4 diff --git a/include/configs/mcx.h b/include/configs/mcx.h new file mode 100644 index 0000000..0940e86 --- /dev/null +++ b/include/configs/mcx.h @@ -0,0 +1,378 @@ +/*
- Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- Based on omap3_evm_config.h
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc.
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+/*
- High Level Configuration Options
- */
+#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP3_MCX /* working with mcx */
+#define MACH_TYPE_MCX 3656 +#define CONFIG_MACH_TYPE MACH_TYPE_MCX
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
+#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h>
+#define CONFIG_OF_LIBFDT +#define CONFIG_FIT
+/*
- Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
- and older u-boot.bin with the new U-Boot SPL.
- */
+#define CONFIG_SYS_TEXT_BASE 0x80008000
+/*
- Display CPU and Board information
- */
+#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO
+/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1)
+#define CONFIG_MISC_INIT_R
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG
+/*
- Size of malloc() pool
- */
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +/*
- DDR related
- */
+#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
+/*
- Hardware drivers
- */
+/*
- NS16550 Configuration
- */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+/*
- select serial console configuration
- */
+#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 */
+/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}+#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION
+/* EHCI */ +#define CONFIG_USB_STORAGE +#define CONFIG_OMAP3_GPIO_5 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_USB_ULPI +#define CONFIG_USB_ULPI_VIEWPORT_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 154 +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 152 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+/* commands to include */ +#include <config_cmd_default.h>
+#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_DRIVER_OMAP34XX_I2C
+/* RTC */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +/*
- Board NAND Info.
- */
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access *//* nand at CS0 */+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
+/* Environment information */ +#define CONFIG_BOOTDELAY 10
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "console=ttyO2,115200n8\0" \
- "mmcargs=setenv bootargs console=${console} " \
"root=/dev/mmcblk0p2 rw " \"rootfstype=ext3 rootwait\0" \- "nandargs=setenv bootargs console=${console} " \
"root=/dev/mtdblock4 rw " \"rootfstype=jffs2\0" \- "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \- "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \"bootm ${loadaddr}\0" \- "nandboot=echo Booting from nand ...; " \
"run nandargs; " \"nand read ${loadaddr} 280000 400000; " \"bootm ${loadaddr}\0" \+#define CONFIG_BOOTCOMMAND \
- "if mmc init; then " \
"if run loadbootscript; then " \"run bootscript; " \"else " \"if run loaduimage; then " \"run mmcboot; " \"else run nandboot; " \"fi; " \"fi; " \- "else run nandboot; fi"
+#define CONFIG_AUTO_COMPLETE +/*
- Miscellaneous configurable options
- */
+#define V_PROMPT "mcx # "
+#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)+#define CONFIG_SYS_MAXARGS 16 /* max number of command */
/* args */+/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
/* address */+/*
- AM3517 has 12 GP timers, they can be driven by the system clock
- (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- This rate is divided by a local divisor.
- */
+#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000
+/*
- Stack sizes
- The stack sizes are set up in start.S using the settings below
- */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+/*
- Physical Memory Map
- */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+/*
- FLASH and environment organization
- */
+/* **** PISMO SUPPORT *** */
+/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT +#define CONFIG_ENV_IS_IN_NAND +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+/*
- CFI FLASH driver setup
- */
+/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
+/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
CONFIG_SYS_MAX_NAND_DEVICE)+#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \GENERATED_GBL_DATA_SIZE)+/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ +#define CONFIG_SPL_MAX_SIZE (45 << 10) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+/* move malloc and bss high to prevent clashing with the main image */ +#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 +#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+/* NAND boot config */ +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
48, 49, 50, 51, 52, 53, 54, 55,\56, 57, 58, 59, 60, 61, 62, 63}+#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
CONFIG_SYS_NAND_ECCSIZE)+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
CONFIG_SYS_NAND_ECCSTEPS)+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+/*
- ethernet support
- */
+#if defined(CONFIG_CMD_NET) +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#endif
+#endif /* __CONFIG_H */