Convert this file to use the driver model PCI API.
Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/ivybridge/lpc.c | 10 ++++---- arch/x86/cpu/ivybridge/pch.c | 35 ++++++++++++++------------ arch/x86/cpu/ivybridge/sata.c | 21 +++++++++++----- arch/x86/include/asm/arch-ivybridge/pch.h | 42 +++++++++++++++++++++++++++---- 4 files changed, 76 insertions(+), 32 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 0cf55c5..12e86cb 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -354,10 +354,10 @@ static void enable_clock_gating(struct udevice *pch) reg16 |= (1 << 2) | (1 << 11); dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
- pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); - pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); + pch_iobp_update(pch, 0xEB007F07, ~0UL, (1 << 31)); + pch_iobp_update(pch, 0xEB004000, ~0UL, (1 << 7)); + pch_iobp_update(pch, 0xEC007F07, ~0UL, (1 << 31)); + pch_iobp_update(pch, 0xEC004000, ~0UL, (1 << 7));
reg32 = readl(RCB_REG(CG)); reg32 |= (1 << 31); @@ -573,7 +573,7 @@ static int lpc_init_extra(struct udevice *dev) pch_power_options(pch);
/* Initialize power management */ - switch (pch_silicon_type()) { + switch (pch_silicon_type(pch)) { case PCH_TYPE_CPT: /* CougarPoint */ cpt_pm_init(pch); break; diff --git a/arch/x86/cpu/ivybridge/pch.c b/arch/x86/cpu/ivybridge/pch.c index bbab646..c7ce408 100644 --- a/arch/x86/cpu/ivybridge/pch.c +++ b/arch/x86/cpu/ivybridge/pch.c @@ -14,32 +14,34 @@ static int pch_revision_id = -1; static int pch_type = -1;
-int pch_silicon_revision(void) +int pch_silicon_revision(struct udevice *dev) { - pci_dev_t dev; + u8 val;
- dev = PCH_LPC_DEV; + if (pch_revision_id < 0) { + dm_pci_read_config8(dev, PCI_REVISION_ID, &val); + pch_revision_id = val; + }
- if (pch_revision_id < 0) - pch_revision_id = x86_pci_read_config8(dev, PCI_REVISION_ID); return pch_revision_id; }
-int pch_silicon_type(void) +int pch_silicon_type(struct udevice *dev) { - pci_dev_t dev; + u8 val;
- dev = PCH_LPC_DEV; + if (pch_type < 0) { + dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val); + pch_type = val; + }
- if (pch_type < 0) - pch_type = x86_pci_read_config8(dev, PCI_DEVICE_ID + 1); return pch_type; }
-int pch_silicon_supported(int type, int rev) +int pch_silicon_supported(struct udevice *dev, int type, int rev) { - int cur_type = pch_silicon_type(); - int cur_rev = pch_silicon_revision(); + int cur_type = pch_silicon_type(dev); + int cur_rev = pch_silicon_revision(dev);
switch (type) { case PCH_TYPE_CPT: @@ -78,7 +80,8 @@ static inline int iobp_poll(void) return 0; }
-void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue, + u32 orvalue) { u32 data;
@@ -86,7 +89,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) writel(address, RCB_REG(IOBPIRI));
/* READ OPCODE */ - if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) + if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) writel(IOBPS_RW_BX, RCB_REG(IOBPS)); else writel(IOBPS_READ_AX, RCB_REG(IOBPS)); @@ -109,7 +112,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) data |= orvalue;
/* WRITE OPCODE */ - if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) + if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) writel(IOBPS_RW_BX, RCB_REG(IOBPS)); else writel(IOBPS_WRITE_AX, RCB_REG(IOBPS)); diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c index 21e11d1..a59d9ed 100644 --- a/arch/x86/cpu/ivybridge/sata.c +++ b/arch/x86/cpu/ivybridge/sata.c @@ -51,7 +51,7 @@ static void common_sata_init(struct udevice *dev, unsigned int port_map) dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183); }
-static void bd82x6x_sata_init(struct udevice *dev) +static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch) { unsigned int port_map, speed_support, port_tx; const void *blob = gd->fdt_blob; @@ -170,11 +170,11 @@ static void bd82x6x_sata_init(struct udevice *dev) /* Set Gen3 Transmitter settings if needed */ port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0); if (port_tx) - pch_iobp_update(SATA_IOBP_SP0G3IR, 0, port_tx); + pch_iobp_update(pch, SATA_IOBP_SP0G3IR, 0, port_tx);
port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0); if (port_tx) - pch_iobp_update(SATA_IOBP_SP1G3IR, 0, port_tx); + pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);
/* Additional Programming Requirements */ sir_write(dev, 0x04, 0x00001600); @@ -199,8 +199,8 @@ static void bd82x6x_sata_init(struct udevice *dev) sir_write(dev, 0xc8, 0x0c0c0c0c); sir_write(dev, 0xd4, 0x10000000);
- pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000); - pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); + pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000); + pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100); }
static void bd82x6x_sata_enable(struct udevice *dev) @@ -226,10 +226,19 @@ static void bd82x6x_sata_enable(struct udevice *dev)
static int bd82x6x_sata_probe(struct udevice *dev) { + struct udevice *pch; + int ret; + + ret = uclass_first_device(UCLASS_PCH, &pch); + if (ret) + return ret; + if (!pch) + return -ENODEV; + if (!(gd->flags & GD_FLG_RELOC)) bd82x6x_sata_enable(dev); else - bd82x6x_sata_init(dev); + bd82x6x_sata_init(dev, pch);
return 0; } diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 629a144..0f1aa01 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -30,11 +30,6 @@
#define SMBUS_IO_BASE 0x0400
-int pch_silicon_revision(void); -int pch_silicon_type(void); -int pch_silicon_supported(int type, int rev); -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); - #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 @@ -470,4 +465,41 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66
+/** + * pch_silicon_revision() - Read silicon revision ID from the PCH + * + * @dev: PCH device + * @return silicon revision ID + */ +int pch_silicon_revision(struct udevice *dev); + +/** + * pch_silicon_revision() - Read silicon device ID from the PCH + * + * @dev: PCH device + * @return silicon device ID + */ +int pch_silicon_type(struct udevice *dev); + +/** + * pch_silicon_supported() - Check if a certain revision is supported + * + * @dev: PCH device + * @type: PCH type + * @rev: Minimum required resion + * @return 0 if not supported, 1 if supported + */ +int pch_silicon_supported(struct udevice *dev, int type, int rev); + +/** + * pch_pch_iobp_update() - Update a pch register + * + * @dev: PCH device + * @address: Address to update + * @andvalue: Value to AND with existing value + * @orvalue: Value to OR with existing value + */ +void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue, + u32 orvalue); + #endif