Thompson, Nick (GE EntSol, Intelligent Platforms) wrote:
Resent due to wrapping in patch 2 (unwrapped patch 1 resent, 3, 4 and 5 seem okay)
Sorry I missed your rev of patch #1. I prefer to see the whole patch set resubmitted instead of parts.
Please also list the version number of the patch set in the subject of at least the 0/n. You commenting on what changed from from version 1 to version 2 is good.
Create initial contents of the include/asm-arm/arch-da8xx directory:
General hardware definitions.
Signed-off-by: Nick Thompson nick.thompson@gefanuc.com
Applies to u-boot-ti
include/asm-arm/arch-da8xx/clock.h | 24 +++ include/asm-arm/arch-da8xx/emac_defs.h | 328 ++++++++++++++++++++++++++++++++ include/asm-arm/arch-da8xx/emif_defs.h | 71 +++++++ include/asm-arm/arch-da8xx/hardware.h | 206 ++++++++++++++++++++ include/asm-arm/arch-da8xx/i2c_defs.h | 95 +++++++++ 5 files changed, 724 insertions(+), 0 deletions(-)
diff --git a/include/asm-arm/arch-da8xx/clock.h b/include/asm-arm/arch-da8xx/clock.h new file mode 100644 index 0000000..a9b74f4 --- /dev/null +++ b/include/asm-arm/arch-da8xx/clock.h @@ -0,0 +1,24 @@ +/*
- Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. nick.thompson@gefanuc.com
Trailing whitespace. Please check globally
- DA8xx clock include header
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
Extra spaces in the last 3 lines
- */
+#ifndef __ASSEMBLER__ +int clk_get(unsigned int id); +#endif
The __ASSEMBLY__ (not __ASSEMBLER__) prefix is used when including headers in assembly files so #defines can be used. This is a mostly empty file. You can remove the __ASSEMBLER__
You should put the timer structure for the first patch here.
diff --git a/include/asm-arm/arch-da8xx/emac_defs.h b/include/asm-arm/arch-da8xx/emac_defs.h new file mode 100644 index 0000000..2da0c41 --- /dev/null +++ b/include/asm-arm/arch-da8xx/emac_defs.h @@ -0,0 +1,328 @@ +/*
- Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net
- Based on:
- dm644x_emac.h
- TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
- Copyright (C) 2005 Texas Instruments.
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
More extra spaces
- Modifications:
- ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
This is not needed for gpl 2. Please remove
- */
+#ifndef _DA8XX_EMAC_H_ +#define _DA8XX_EMAC_H_
+#include <asm/arch/hardware.h>
+#define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE +#define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE +#define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE +#define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE
+/* MDIO module input frequency */ +#define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID)
+/* MDIO clock output frequency */ +#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
+/* Ethernet Min/Max packet size */ +#define EMAC_MIN_ETHERNET_PKT_SIZE 60 +#define EMAC_MAX_ETHERNET_PKT_SIZE 1518 +#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */
This exceeds the 80 chars per line. checkpatch.pl will help you find the others. Please apply globally.
+/* Number of RX packet buffers
- NOTE: Only 1 buffer supported as of now
- */
+#define EMAC_MAX_RX_BUFFERS 10
Extra line, remove
+/***********************************************
- ******** Internally used macros ***************
- ***********************************************/
Convert to multi-line comment style mentioned in patch 1 If these are really internal macros, they should not be included here. Maybe you should move them to the 'C' file?
+#define EMAC_CH_TX 1 +#define EMAC_CH_RX 0
+/* Each descriptor occupies 4 words, lets start RX desc's at 0 and
- reserve space for 64 descriptors max
Multi-line comment
- */
+#define EMAC_RX_DESC_BASE 0x0 +#define EMAC_TX_DESC_BASE 0x1000
+/* EMAC Teardown value */ +#define EMAC_TEARDOWN_VALUE 0xfffffffc
+/* MII Status Register */ +#define MII_STATUS_REG 1
+/* Number of statistics registers */ +#define EMAC_NUM_STATS 36
+/* EMAC Descriptor */ +typedef volatile struct _emac_desc
The volatile is not needed. The read / write access is not direct but rather through the readl/writel (or appropriate datalength) function
+{
- u_int32_t next; /* Pointer to next descriptor in chain */
- u_int8_t *buffer; /* Pointer to data buffer */
- u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
- u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
+} emac_desc;
+/* CPPI bit positions */ +#define EMAC_CPPI_SOP_BIT (0x80000000) +#define EMAC_CPPI_EOP_BIT (0x40000000) +#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) +#define EMAC_CPPI_EOQ_BIT (0x10000000) +#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) +#define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
Extra line
+#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
+#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) +#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) +#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
+#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) +#define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
Extra line
+#define MDIO_CONTROL_IDLE (0x80000000) +#define MDIO_CONTROL_ENABLE (0x40000000) +#define MDIO_CONTROL_FAULT_ENABLE (0x40000) +#define MDIO_CONTROL_FAULT (0x80000) +#define MDIO_USERACCESS0_GO (0x80000000) +#define MDIO_USERACCESS0_WRITE_READ (0x0) +#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) +#define MDIO_USERACCESS0_ACK (0x20000000)
The '( ' .. ')' are not needed around the #define-ed immediates. They can be removed.
+/* Ethernet MAC Registers Structure */ +typedef struct {
- dv_reg TXIDVER;
- dv_reg TXCONTROL;
- dv_reg TXTEARDOWN;
- u_int8_t RSVD0[4];
- dv_reg RXIDVER;
- dv_reg RXCONTROL;
- dv_reg RXTEARDOWN;
- u_int8_t RSVD1[100];
- dv_reg TXINTSTATRAW;
- dv_reg TXINTSTATMASKED;
- dv_reg TXINTMASKSET;
- dv_reg TXINTMASKCLEAR;
- dv_reg MACINVECTOR;
- u_int8_t RSVD2[12];
- dv_reg RXINTSTATRAW;
- dv_reg RXINTSTATMASKED;
- dv_reg RXINTMASKSET;
- dv_reg RXINTMASKCLEAR;
- dv_reg MACINTSTATRAW;
- dv_reg MACINTSTATMASKED;
- dv_reg MACINTMASKSET;
- dv_reg MACINTMASKCLEAR;
- u_int8_t RSVD3[64];
- dv_reg RXMBPENABLE;
- dv_reg RXUNICASTSET;
- dv_reg RXUNICASTCLEAR;
- dv_reg RXMAXLEN;
- dv_reg RXBUFFEROFFSET;
- dv_reg RXFILTERLOWTHRESH;
- u_int8_t RSVD4[8];
- dv_reg RX0FLOWTHRESH;
- dv_reg RX1FLOWTHRESH;
- dv_reg RX2FLOWTHRESH;
- dv_reg RX3FLOWTHRESH;
- dv_reg RX4FLOWTHRESH;
- dv_reg RX5FLOWTHRESH;
- dv_reg RX6FLOWTHRESH;
- dv_reg RX7FLOWTHRESH;
- dv_reg RX0FREEBUFFER;
- dv_reg RX1FREEBUFFER;
- dv_reg RX2FREEBUFFER;
- dv_reg RX3FREEBUFFER;
- dv_reg RX4FREEBUFFER;
- dv_reg RX5FREEBUFFER;
- dv_reg RX6FREEBUFFER;
- dv_reg RX7FREEBUFFER;
- dv_reg MACCONTROL;
- dv_reg MACSTATUS;
- dv_reg EMCONTROL;
- dv_reg FIFOCONTROL;
- dv_reg MACCONFIG;
- dv_reg SOFTRESET;
- u_int8_t RSVD5[88];
- dv_reg MACSRCADDRLO;
- dv_reg MACSRCADDRHI;
- dv_reg MACHASH1;
- dv_reg MACHASH2;
- dv_reg BOFFTEST;
- dv_reg TPACETEST;
- dv_reg RXPAUSE;
- dv_reg TXPAUSE;
- u_int8_t RSVD6[16];
- dv_reg RXGOODFRAMES;
- dv_reg RXBCASTFRAMES;
- dv_reg RXMCASTFRAMES;
- dv_reg RXPAUSEFRAMES;
- dv_reg RXCRCERRORS;
- dv_reg RXALIGNCODEERRORS;
- dv_reg RXOVERSIZED;
- dv_reg RXJABBER;
- dv_reg RXUNDERSIZED;
- dv_reg RXFRAGMENTS;
- dv_reg RXFILTERED;
- dv_reg RXQOSFILTERED;
- dv_reg RXOCTETS;
- dv_reg TXGOODFRAMES;
- dv_reg TXBCASTFRAMES;
- dv_reg TXMCASTFRAMES;
- dv_reg TXPAUSEFRAMES;
- dv_reg TXDEFERRED;
- dv_reg TXCOLLISION;
- dv_reg TXSINGLECOLL;
- dv_reg TXMULTICOLL;
- dv_reg TXEXCESSIVECOLL;
- dv_reg TXLATECOLL;
- dv_reg TXUNDERRUN;
- dv_reg TXCARRIERSENSE;
- dv_reg TXOCTETS;
- dv_reg FRAME64;
- dv_reg FRAME65T127;
- dv_reg FRAME128T255;
- dv_reg FRAME256T511;
- dv_reg FRAME512T1023;
- dv_reg FRAME1024TUP;
- dv_reg NETOCTETS;
- dv_reg RXSOFOVERRUNS;
- dv_reg RXMOFOVERRUNS;
- dv_reg RXDMAOVERRUNS;
- u_int8_t RSVD7[624];
- dv_reg MACADDRLO;
- dv_reg MACADDRHI;
- dv_reg MACINDEX;
- u_int8_t RSVD8[244];
- dv_reg TX0HDP;
- dv_reg TX1HDP;
- dv_reg TX2HDP;
- dv_reg TX3HDP;
- dv_reg TX4HDP;
- dv_reg TX5HDP;
- dv_reg TX6HDP;
- dv_reg TX7HDP;
- dv_reg RX0HDP;
- dv_reg RX1HDP;
- dv_reg RX2HDP;
- dv_reg RX3HDP;
- dv_reg RX4HDP;
- dv_reg RX5HDP;
- dv_reg RX6HDP;
- dv_reg RX7HDP;
- dv_reg TX0CP;
- dv_reg TX1CP;
- dv_reg TX2CP;
- dv_reg TX3CP;
- dv_reg TX4CP;
- dv_reg TX5CP;
- dv_reg TX6CP;
- dv_reg TX7CP;
- dv_reg RX0CP;
- dv_reg RX1CP;
- dv_reg RX2CP;
- dv_reg RX3CP;
- dv_reg RX4CP;
- dv_reg RX5CP;
- dv_reg RX6CP;
- dv_reg RX7CP;
+} emac_regs;
Lowercase the elements Please apply this globally.
+/* EMAC Wrapper Registers Structure */ +typedef struct {
- dv_reg REV;
- dv_reg SOFTRESET;
- dv_reg INTCONTROL;
- dv_reg C0RXTHRESHEN;
- dv_reg C0RXEN;
- dv_reg C0TXEN;
- dv_reg C0MISCEN;
- dv_reg C1RXTHRESHEN;
- dv_reg C1RXEN;
- dv_reg C1TXEN;
- dv_reg C1MISCEN;
- dv_reg C2RXTHRESHEN;
- dv_reg C2RXEN;
- dv_reg C2TXEN;
- dv_reg C2MISCEN;
- dv_reg C0RXTHRESHSTAT;
- dv_reg C0RXSTAT;
- dv_reg C0TXSTAT;
- dv_reg C0MISCSTAT;
- dv_reg C1RXTHRESHSTAT;
- dv_reg C1RXSTAT;
- dv_reg C1TXSTAT;
- dv_reg C1MISCSTAT;
- dv_reg C2RXTHRESHSTAT;
- dv_reg C2RXSTAT;
- dv_reg C2TXSTAT;
- dv_reg C2MISCSTAT;
- dv_reg C0RXIMAX;
- dv_reg C0TXIMAX;
- dv_reg C1RXIMAX;
- dv_reg C1TXIMAX;
- dv_reg C2RXIMAX;
- dv_reg C2TXIMAX;
+} ewrap_regs;
Extra line
+/* EMAC MDIO Registers Structure */ +typedef struct {
- dv_reg VERSION;
- dv_reg CONTROL;
- dv_reg ALIVE;
- dv_reg LINK;
- dv_reg LINKINTRAW;
- dv_reg LINKINTMASKED;
- u_int8_t RSVD0[8];
- dv_reg USERINTRAW;
- dv_reg USERINTMASKED;
- dv_reg USERINTMASKSET;
- dv_reg USERINTMASKCLEAR;
- u_int8_t RSVD1[80];
- dv_reg USERACCESS0;
- dv_reg USERPHYSEL0;
- dv_reg USERACCESS1;
- dv_reg USERPHYSEL1;
+} mdio_regs;
+typedef struct +{
- char name[64];
- int (*init)(int phy_addr);
- int (*is_phy_connected)(int phy_addr);
- int (*get_link_speed)(int phy_addr);
- int (*auto_negotiate)(int phy_addr);
+} phy_t;
+#endif /* _DA8XX_EMAC_H_ */ diff --git a/include/asm-arm/arch-da8xx/emif_defs.h b/include/asm-arm/arch-da8xx/emif_defs.h new file mode 100644 index 0000000..c91e30c --- /dev/null +++ b/include/asm-arm/arch-da8xx/emif_defs.h @@ -0,0 +1,71 @@ +/*
- Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#ifndef _EMIF_DEFS_H_ +#define _EMIF_DEFS_H_
+#include <asm/arch/hardware.h>
+typedef struct {
- dv_reg ERCSR;
- dv_reg AWCCR;
- dv_reg SDBCR;
- dv_reg SDRCR;
- dv_reg AB1CR;
- dv_reg AB2CR;
- dv_reg AB3CR;
- dv_reg AB4CR;
- dv_reg SDTIMR;
- dv_reg DDRSR;
- dv_reg DDRPHYCR;
- dv_reg DDRPHYSR;
- dv_reg TOTAR;
- dv_reg TOTACTR;
- dv_reg DDRPHYID_REV;
- dv_reg SDSRETR;
- dv_reg EIRR;
- dv_reg EIMR;
- dv_reg EIMSR;
- dv_reg EIMCR;
- dv_reg IOCTRLR;
- dv_reg IOSTATR;
- u_int8_t RSVD0[8];
- dv_reg NANDFCR;
- dv_reg NANDFSR;
- u_int8_t RSVD1[8];
- dv_reg NANDF1ECC;
- dv_reg NANDF2ECC;
- dv_reg NANDF3ECC;
- dv_reg NANDF4ECC;
- u_int8_t RSVD2[60];
- dv_reg NAND4BITECCLOAD;
- dv_reg NAND4BITECC1;
- dv_reg NAND4BITECC2;
- dv_reg NAND4BITECC3;
- dv_reg NAND4BITECC4;
- dv_reg NANDERRADD1;
- dv_reg NANDERRADD2;
- dv_reg NANDERRVAL1;
- dv_reg NANDERRVAL2;
+} emif_registers;
+typedef emif_registers *emifregs; +#endif diff --git a/include/asm-arm/arch-da8xx/hardware.h b/include/asm-arm/arch-da8xx/hardware.h new file mode 100644 index 0000000..ec2176d --- /dev/null +++ b/include/asm-arm/arch-da8xx/hardware.h @@ -0,0 +1,206 @@ +/*
- Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc
The author usually goes on the next line. But if this was the original file, do not modify.
- Based on hardware.h for DaVinci. Original Copyrights follow.
- Sergey Kubushyn ksi@koi8.net
- Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net
- Based on:
- linux/include/asm-arm/arch-davinci/hardware.h
- Copyright (C) 2006 Texas Instruments.
- This program is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published by the
- Free Software Foundation; either version 2 of the License, or (at your
- option) any later version.
- THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 675 Mass Ave, Cambridge, MA 02139, USA.
If checkpatch complains about the line exceeding 80 chars, remove the leading tabs of the copyrite
- */
+#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H
Change this to a less generic name. Something like __DA8XX_HARDWARE__
+#include <config.h>
+#ifndef __ASSEMBLY__
+#include <asm/sizes.h>
+#define REG(addr) (*(volatile unsigned int *)(addr)) +#define REG_P(addr) ((volatile unsigned int *)(addr))
+typedef volatile unsigned int dv_reg; +typedef volatile unsigned int * dv_reg_p;
This typedef and macros will go way when you convert to using readl/writel
+#endif
+/*
- Base register addresses
- */
The '(' .. ')' should be removed from the #define immediates.
+#define DAVINCI_UART0_BASE (0x01c42000) +#define DAVINCI_UART1_BASE (0x01d0c000) +#define DAVINCI_UART2_BASE (0x01d0d000) +#define DAVINCI_I2C0_BASE (0x01c22000) +#define DAVINCI_I2C1_BASE (0x01e28000) +#define DAVINCI_TIMER0_BASE (0x01c20000)
space after ..BASE
+#define DAVINCI_TIMER1_BASE (0x01c21000)
space after ..BASE
+#define DAVINCI_WDOG_BASE (0x01c21000) +#define DAVINCI_PLL_CNTRL0_BASE (0x01c11000)
space after ..BASE
+#define DAVINCI_PSC0_BASE (0x01c10000) +#define DAVINCI_PSC1_BASE (0x01e27000) +#define DAVINCI_SPI0_BASE (0x01c41000) +#define DAVINCI_USB_OTG_BASE (0x01e00000) +#define DAVINCI_SPI1_BASE (0x01e12000) +#define DAVINCI_GPIO_BASE (0x01e26000) +#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01e23000) +#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01e22000) +#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01e20000) +#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01e24000) +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x68000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x40000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x60000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x62000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE (0x64000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE (0x66000000) +#define DAVINCI_DDR_EMIF_CTRL_BASE (0xb0000000) +#define DAVINCI_DDR_EMIF_DATA_BASE (0xc0000000) +#define DAVINCI_INTC_BASE (0xfffee000) +#define DAVINCI_BOOTCFG_BASE (0x01c14000)
+/* Clock IDs */ +#define DAVINCI_PLLM_CLKID (0xFF + 0) +#define DAVINCI_PLLC_CLKID (0xFF + 1) +#define DAVINCI_AUXCLK_CLKID (0xFF + 2) +#define DAVINCI_MDIO_CLKID 4 +#define DAVINCI_SPI0_CLKID 2 +#define DAVINCI_UART2_CLKID 2 +#define DAVINCI_ARM_CLKID 6
spaces before 6
+/* Power and Sleep Controller (PSC) Domains */ +#define DAVINCI_GPSC_ARMDOMAIN 0 +#define DAVINCI_GPSC_DSPDOMAIN 1
+/* LPSCs in PSC0 */ +#define DAVINCI_LPSC_TPCC 0 +#define DAVINCI_LPSC_TPTC0 1 +#define DAVINCI_LPSC_TPTC1 2 +#define DAVINCI_LPSC_AEMIF 3 +#define DAVINCI_LPSC_SPI0 4 +#define DAVINCI_LPSC_MMC_SD 5
space after SD
+#define DAVINCI_LPSC_AINTC 6 +#define DAVINCI_LPSC_ARM_RAM_ROM 7 +#define DAVINCI_LPSC_SECCTL_KEYMGR 8 +#define DAVINCI_LPSC_UART0 9 +#define DAVINCI_LPSC_SCR0 10 +#define DAVINCI_LPSC_SCR1 11 +#define DAVINCI_LPSC_SCR2 12 +#define DAVINCI_LPSC_DMAX 13 +#define DAVINCI_LPSC_ARM 14 +#define DAVINCI_LPSC_GEM 15
+/* for LPSCs in PSC1, 32 + actual id is being used for differentiation */ +#define DAVINCI_LPSC_USB11 (32 + 1)
Consider making the 32 a #define
+#define DAVINCI_LPSC_USB20 (32 + 2) +#define DAVINCI_LPSC_GPIO (32 + 3) +#define DAVINCI_LPSC_UHPI (32 + 4) +#define DAVINCI_LPSC_EMAC (32 + 5) +#define DAVINCI_LPSC_DDR_EMIF (32 + 6) +#define DAVINCI_LPSC_McASP0 (32 + 7) +#define DAVINCI_LPSC_McASP1 (32 + 8) +#define DAVINCI_LPSC_McASP2 (32 + 9)
space ater the last 3 lines 0,1,2
+#define DAVINCI_LPSC_SPI1 (32 + 10) +#define DAVINCI_LPSC_I2C1 (32 + 11) +#define DAVINCI_LPSC_UART1 (32 + 12) +#define DAVINCI_LPSC_UART2 (32 + 13) +#define DAVINCI_LPSC_LCDC (32 + 16) +#define DAVINCI_LPSC_ePWM (32 + 17) +#define DAVINCI_LPSC_eCAP (32 + 20) +#define DAVINCI_LPSC_eQEP (32 + 21) +#define DAVINCI_LPSC_SCR_P0 (32 + 22) +#define DAVINCI_LPSC_SCR_P1 (32 + 23)
space after the last 2 lines This is a general problem. Please check that your #defines just have tab between the identifier and the value.
+#define DAVINCI_LPSC_CR_P3 (32 + 26) +#define DAVINCI_LPSC_L3_CBA_RAM (32 + 31)
+/* Some PSC defines */
+#define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00) +#define PSC0_MDSTAT (DAVINCI_PSC0_BASE + 0x800) +#define PSC0_PTCMD (DAVINCI_PSC0_BASE + 0x120) +#define PSC0_PTSTAT (DAVINCI_PSC0_BASE + 0x128)
+#define PSC1_MDCTL (DAVINCI_PSC1_BASE + 0xa00) +#define PSC1_MDSTAT (DAVINCI_PSC1_BASE + 0x800) +#define PSC1_PTCMD (DAVINCI_PSC1_BASE + 0x120) +#define PSC1_PTSTAT (DAVINCI_PSC1_BASE + 0x128)
+/* Some PLL defines */ +#define PLL0_PLLCTL (DAVINCI_PLL_CNTRL0_BASE + 0x100) +#define PLL0_PLLM (DAVINCI_PLL_CNTRL0_BASE + 0x110) +#define PLL0_PREDIV (DAVINCI_PLL_CNTRL0_BASE + 0x114) +#define PLL0_POSTDIV (DAVINCI_PLL_CNTRL0_BASE + 0x128) +#define PLL0_DIV1 (DAVINCI_PLL_CNTRL0_BASE + 0x118) +#define PLL0_DIV2 (DAVINCI_PLL_CNTRL0_BASE + 0x11c) +#define PLL0_DIV3 (DAVINCI_PLL_CNTRL0_BASE + 0x120) +#define PLL0_DIV4 (DAVINCI_PLL_CNTRL0_BASE + 0x160) +#define PLL0_DIV5 (DAVINCI_PLL_CNTRL0_BASE + 0x164) +#define PLL0_DIV6 (DAVINCI_PLL_CNTRL0_BASE + 0x168) +#define PLL0_DIV7 (DAVINCI_PLL_CNTRL0_BASE + 0x16c) +#define PLL0_DIV8 (DAVINCI_PLL_CNTRL0_BASE + 0x170) +#define PLL0_DIV9 (DAVINCI_PLL_CNTRL0_BASE + 0x114)
+/* Boot config */ +#define PINMUX0 (DAVINCI_BOOTCFG_BASE + 0x120) +#define PINMUX1 (DAVINCI_BOOTCFG_BASE + 0x124) +#define PINMUX2 (DAVINCI_BOOTCFG_BASE + 0x128) +#define PINMUX3 (DAVINCI_BOOTCFG_BASE + 0x12c) +#define PINMUX4 (DAVINCI_BOOTCFG_BASE + 0x130) +#define PINMUX5 (DAVINCI_BOOTCFG_BASE + 0x134) +#define PINMUX6 (DAVINCI_BOOTCFG_BASE + 0x138) +#define PINMUX7 (DAVINCI_BOOTCFG_BASE + 0x13c) +#define PINMUX8 (DAVINCI_BOOTCFG_BASE + 0x140) +#define PINMUX9 (DAVINCI_BOOTCFG_BASE + 0x144) +#define PINMUX10 (DAVINCI_BOOTCFG_BASE + 0x148) +#define PINMUX11 (DAVINCI_BOOTCFG_BASE + 0x14c) +#define PINMUX12 (DAVINCI_BOOTCFG_BASE + 0x150) +#define PINMUX13 (DAVINCI_BOOTCFG_BASE + 0x154) +#define PINMUX14 (DAVINCI_BOOTCFG_BASE + 0x158) +#define PINMUX15 (DAVINCI_BOOTCFG_BASE + 0x15C) +#define PINMUX16 (DAVINCI_BOOTCFG_BASE + 0x160) +#define PINMUX17 (DAVINCI_BOOTCFG_BASE + 0x164) +#define PINMUX18 (DAVINCI_BOOTCFG_BASE + 0x168) +#define PINMUX19 (DAVINCI_BOOTCFG_BASE + 0x16c) +#define SUSPSRC (DAVINCI_BOOTCFG_BASE + 0x170) +#define CFGCHIP0 (DAVINCI_BOOTCFG_BASE + 0x17c) +#define CFGCHIP2 (DAVINCI_BOOTCFG_BASE + 0x184)
+/* Interrupt controller */ +#define INTC_GLB_EN (DAVINCI_INTC_BASE + 0x10) +#define INTC_HINT_EN (DAVINCI_INTC_BASE + 0x1500) +#define INTC_EN_CLR0 (DAVINCI_INTC_BASE + 0x380)
+/* GPIO */ +#define GPIO_BANK4_ADDR 0x01E26000 +#define GPIO_BANK4_REG_DIR_ADDR ( GPIO_BANK4_ADDR + 0x60 ) +#define GPIO_BANK4_REG_OPDATA_ADDR ( GPIO_BANK4_ADDR + 0x64 ) +#define GPIO_BANK4_REG_SET_ADDR ( GPIO_BANK4_ADDR + 0x68 ) +#define GPIO_BANK4_REG_CLR_ADDR ( GPIO_BANK4_ADDR + 0x6C )
Extra spaces after '(' and before ')' should be removed
+#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-da8xx/i2c_defs.h b/include/asm-arm/arch-da8xx/i2c_defs.h new file mode 100644 index 0000000..714211f --- /dev/null +++ b/include/asm-arm/arch-da8xx/i2c_defs.h @@ -0,0 +1,95 @@ +/*
- (C) Copyright 2004
- Texas Instruments, <www.ti.com>
I believe TI copywrite have the these lines combined into 1. Please check.
- Some changes copyright (C) 2007 Sergey Kubushyn ksi@koi8.net
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#ifndef _DAVINCI_I2C_H_ +#define _DAVINCI_I2C_H_
+#define I2C_WRITE 0 +#define I2C_READ 1
+#define I2C_BASE 0x01c22000
+#define I2C_OA (I2C_BASE + 0x00) +#define I2C_IE (I2C_BASE + 0x04) +#define I2C_STAT (I2C_BASE + 0x08) +#define I2C_SCLL (I2C_BASE + 0x0c) +#define I2C_SCLH (I2C_BASE + 0x10) +#define I2C_CNT (I2C_BASE + 0x14) +#define I2C_DRR (I2C_BASE + 0x18) +#define I2C_SA (I2C_BASE + 0x1c) +#define I2C_DXR (I2C_BASE + 0x20) +#define I2C_CON (I2C_BASE + 0x24) +#define I2C_IV (I2C_BASE + 0x28) +#define I2C_PSC (I2C_BASE + 0x30)
+/* I2C masks */
+/* I2C Interrupt Enable Register (I2C_IE): */ +#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */ +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
These comment cause lines exceeding 80 chars. This is a general problem Please fix where appropriate
+/* I2C Status Register (I2C_STAT): */
+#define I2C_STAT_BB (1 << 12) /* Bus busy */ +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */ +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
This value likely doesn't not align with the ones above it. Please fix if it doesn't.
Extra line
+/* I2C Interrupt Code Register (I2C_INTCODE): */
+#define I2C_INTCODE_MASK 7 +#define I2C_INTCODE_NONE 0 +#define I2C_INTCODE_AL 1 /* Arbitration lost */ +#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ +#define I2C_INTCODE_ARDY 3 /* Register access ready */ +#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ +#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ +#define I2C_INTCODE_SCD 6 /* Stop condition detect */
+/* I2C Configuration Register (I2C_CON): */
+#define I2C_CON_EN (1 << 5) /* I2C module enable */ +#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */ +#define I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ +#define I2C_CON_XA (1 << 8) /* Expand address */ +#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */ +#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */ +#define I2C_CON_FREE (1 << 14) /* Free run on emulation */
+#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */
+#endif _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot