On Thu, Nov 5, 2020 at 9:32 PM Simon Glass sjg@chromium.org wrote:
Add a file containing defaults for these, using the existing CONFIG options. This file must be included with #include since it needs to are not passed through the C preprocessor.
it needs to be ?
Enable the driver for all x86 boards that generate SMBIOS tables. Disable it for coral since it has its own driver.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v6:
- Add new patch to provide default SMBIOS manufacturer/product
arch/Kconfig | 2 ++ arch/x86/dts/bayleybay.dts | 2 ++ arch/x86/dts/baytrail_som-db5800-som-6867.dts | 2 ++ arch/x86/dts/cherryhill.dts | 2 ++ arch/x86/dts/chromebook_link.dts | 2 ++ arch/x86/dts/chromebook_samus.dts | 2 ++ arch/x86/dts/chromebox_panther.dts | 2 ++ arch/x86/dts/conga-qeval20-qa3-e3845.dts | 2 ++ arch/x86/dts/cougarcanyon2.dts | 2 ++ arch/x86/dts/crownbay.dts | 2 ++ arch/x86/dts/dfi-bt700.dtsi | 2 ++ arch/x86/dts/edison.dts | 2 ++ arch/x86/dts/minnowmax.dts | 2 ++ arch/x86/dts/qemu-x86_i440fx.dts | 2 ++ arch/x86/dts/qemu-x86_q35.dts | 2 ++ arch/x86/dts/smbios.dtsi | 32 +++++++++++++++++++ configs/chromebook_coral_defconfig | 2 +- 17 files changed, 63 insertions(+), 1 deletion(-) create mode 100644 arch/x86/dts/smbios.dtsi
diff --git a/arch/Kconfig b/arch/Kconfig index 3b9fcce980a..041e179256a 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -198,6 +198,8 @@ config X86 imply RTC_MC146818 imply IRQ imply ACPIGEN if !QEMU
imply SYSINFO if GENERATE_SMBIOS_TABLEimply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE # Thing to enable for when SPL/TPL are enabled: SPL imply SPL_DMdiff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index d0168e88dbd..70e57984031 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -16,6 +16,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
/ { model = "Intel Bayley Bay"; compatible = "intel,bayleybay", "intel,baytrail"; diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts index 5abbc66ce98..a7dc03b6458 100644 --- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -16,6 +16,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
/ { model = "Advantech SOM-DB5800-SOM-6867"; compatible = "advantech,som-db5800-som-6867", "intel,baytrail"; diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts index 37146fde2ba..2ce7f1aa91a 100644 --- a/arch/x86/dts/cherryhill.dts +++ b/arch/x86/dts/cherryhill.dts @@ -14,6 +14,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
/ { model = "Intel Cherry Hill"; compatible = "intel,cherryhill", "intel,braswell"; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 09488f13b58..e529c4b63e0 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -11,6 +11,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
/ { model = "Google Link"; compatible = "google,link", "intel,celeron-ivybridge"; diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts index d8e04a66985..adaeb1ea355 100644 --- a/arch/x86/dts/chromebook_samus.dts +++ b/arch/x86/dts/chromebook_samus.dts @@ -9,6 +9,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
#ifdef CONFIG_CHROMEOS_VBOOT #include "chromeos-x86.dtsi" #include "flashmap-x86-ro.dtsi" diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index bcd4c4d9c1b..77b6ac9ab96 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -6,6 +6,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
/ { model = "Google Panther"; compatible = "google,panther", "intel,haswell"; diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 70b8c045193..bbea99da2c9 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -16,6 +16,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
/ { model = "congatec-QEVAL20-QA3-E3845"; compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail"; diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts index c6ba811e059..602523333e3 100644 --- a/arch/x86/dts/cougarcanyon2.dts +++ b/arch/x86/dts/cougarcanyon2.dts @@ -14,6 +14,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
/ { model = "Intel Cougar Canyon 2"; compatible = "intel,cougarcanyon2", "intel,chiefriver"; diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index f492c35875b..a7166a97491 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -15,6 +15,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
/ { model = "Intel Crown Bay"; compatible = "intel,crownbay", "intel,queensbay"; diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi index e9930cb0436..7d7b8357d92 100644 --- a/arch/x86/dts/dfi-bt700.dtsi +++ b/arch/x86/dts/dfi-bt700.dtsi @@ -13,6 +13,8 @@ #include "rtc.dtsi" #include "tsc_timer.dtsi"
+#include "smbios.dtsi"
/ { config { silent_console = <0>; diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts index e2f9469de32..bc84bc892e7 100644 --- a/arch/x86/dts/edison.dts +++ b/arch/x86/dts/edison.dts @@ -12,6 +12,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
/ { model = "Intel Edison"; compatible = "intel,edison"; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index f4cdb2c3cd2..133d55bc20f 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -15,6 +15,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
/ { model = "Intel Minnowboard Max"; compatible = "intel,minnowmax", "intel,baytrail"; diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts index 2e5210d4ee6..c33a11d593f 100644 --- a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -14,6 +14,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
/ { model = "QEMU x86 (I440FX)"; compatible = "qemu,x86"; diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index e8f55b19a26..9faae7fb569 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -24,6 +24,8 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi"
+#include "smbios.dtsi"
/ { model = "QEMU x86 (Q35)"; compatible = "qemu,x86"; diff --git a/arch/x86/dts/smbios.dtsi b/arch/x86/dts/smbios.dtsi new file mode 100644 index 00000000000..9fa8c638a58 --- /dev/null +++ b/arch/x86/dts/smbios.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Default SMBIOS information. Include this in your board .dts file if you want
- these defaults.
- Copyright 2020 Google LLC
- */
+#include <config.h>
+/ {
smbios: smbios {compatible = "u-boot,sysinfo-smbios";smbios {system {manufacturer = CONFIG_SYS_VENDOR;product = CONFIG_SYS_BOARD;};baseboard {manufacturer = CONFIG_SYS_VENDOR;product = CONFIG_SYS_BOARD;};chassis {manufacturer = CONFIG_SYS_VENDOR;/* chassis product is not set by default */};};};+}; diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index d960793d9a9..51f892fb13d 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -99,7 +99,7 @@ CONFIG_SOUND_MAX98357A=y CONFIG_SOUND_RT5677=y CONFIG_SPI=y CONFIG_ICH_SPI=y -CONFIG_SYSINFO=y +# CONFIG_SYSINFO_SMBIOS is not set CONFIG_TPL_SYSRESET=y # CONFIG_TPM_V1 is not set CONFIG_TPM2_CR50_I2C=y
Reviewed-by: Bin Meng bmeng.cn@gmail.com