On Wed, Sep 1, 2021 at 2:46 AM nicholas_zheng@outlook.com wrote:
From: weichangzheng nicholas_zheng@outlook.com
This adds platform code and the device tree for the Phytium Pomelo Board. The initial support comprises the UART and the PCIE.
Signed-off-by: weichangzheng nicholas_zheng@outlook.com Changes since v1: updated to DT Changes since v2: Modify some explicit types and macro Changes since v3: Modify some SDRAM related macro definitions and distro_bootcmd Changes since v4: Modify distro_bootcmd
arch/arm/Kconfig | 20 ++++ arch/arm/dts/Makefile | 1 + arch/arm/dts/phytium-pomelo.dts | 113 ++++++++++++++++++++++ board/phytium/pomelo/Kconfig | 12 +++ board/phytium/pomelo/MAINTAINERS | 8 ++ board/phytium/pomelo/Makefile | 14 +++ board/phytium/pomelo/cpu.h | 73 ++++++++++++++ board/phytium/pomelo/ddr.c | 161 +++++++++++++++++++++++++++++++ board/phytium/pomelo/pcie.c | 60 ++++++++++++ board/phytium/pomelo/pll.c | 73 ++++++++++++++ board/phytium/pomelo/pomelo.c | 118 ++++++++++++++++++++++ board/phytium/pomelo/sec.c | 37 +++++++ configs/pomelo_defconfig | 18 ++++ include/configs/pomelo.h | 44 +++++++++ 14 files changed, 752 insertions(+) create mode 100644 arch/arm/dts/phytium-pomelo.dts create mode 100644 board/phytium/pomelo/Kconfig create mode 100644 board/phytium/pomelo/MAINTAINERS create mode 100644 board/phytium/pomelo/Makefile create mode 100644 board/phytium/pomelo/cpu.h create mode 100644 board/phytium/pomelo/ddr.c create mode 100644 board/phytium/pomelo/pcie.c create mode 100644 board/phytium/pomelo/pll.c create mode 100644 board/phytium/pomelo/pomelo.c create mode 100644 board/phytium/pomelo/sec.c create mode 100644 configs/pomelo_defconfig create mode 100644 include/configs/pomelo.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0448787b8b..029af85fcb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1818,6 +1818,25 @@ config TARGET_DURIAN Support for durian platform. It has 2GB Sdram, uart and pcie.
+config TARGET_POMELO
bool "Support Phytium Pomelo Platform"select ARM64select DMselect AHCIselect SCSI_AHCIselect AHCI_PCIselect BLKselect PCIselect DM_PCIselect SCSIselect DM_SCSIselect DM_SERIALselect DM_ETH if NETimply CMD_PCIhelpSupport for pomelo platform.It has 8GB Sdram, uart and pcie.config TARGET_PRESIDIO_ASIC bool "Support Cortina Presidio ASIC Platform" select ARM64 @@ -2038,6 +2057,7 @@ source "board/toradex/colibri_pxa270/Kconfig" source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" +source "board/phytium/pomelo/Kconfig" source "board/xen/xenguest_arm64/Kconfig" source "board/keymile/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9fb38682e6..45d0340bd3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1107,6 +1107,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb +dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
diff --git a/arch/arm/dts/phytium-pomelo.dts b/arch/arm/dts/phytium-pomelo.dts new file mode 100644 index 0000000000..3869475902 --- /dev/null +++ b/arch/arm/dts/phytium-pomelo.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- dts file for Phytium Pomelo board
- Copyright (C) 2021, Phytium Ltd.
- lixinde lixinde@phytium.com.cn
- weichangzheng weichangzheng@phytium.com.cn
- */
+/dts-v1/;
+/ {
model = "Phytium Pomelo";compatible = "phytium,pomelo";
There should be an SoC compatible string too.
#address-cells = <2>;#size-cells = <2>;aliases {serial0 = &uart0;};cpus {#address-cells = <0x2>;#size-cells = <0x0>;cpu0: cpu@0 {device_type = "cpu";compatible = "arm,armv8";
arm,armv8 is only valid for s/w models.
reg = <0x0 0x0>;enable-method = "psci";numa-node-id = <0>;
The only id used is 0, do you need this?
};cpu1: cpu@1 {device_type = "cpu";compatible = "arm,armv8";reg = <0x0 0x1>;enable-method = "psci";numa-node-id = <0>;};cpu2: cpu@4 {
Wrong unit-address.
device_type = "cpu";compatible = "arm,armv8";reg = <0x0 0x100>;enable-method = "psci";numa-node-id = <0>;};cpu3: cpu@5 {device_type = "cpu";compatible = "arm,armv8";reg = <0x0 0x101>;enable-method = "psci";numa-node-id = <0>;};cpu4: cpu@8 {device_type = "cpu";compatible = "arm,armv8";reg = <0x0 0x200>;enable-method = "psci";numa-node-id = <0>;};cpu5: cpu@9 {device_type = "cpu";compatible = "arm,armv8";reg = <0x0 0x201>;enable-method = "psci";numa-node-id = <0>;};cpu6: cpu@12 {device_type = "cpu";compatible = "arm,armv8";reg = <0x0 0x300>;enable-method = "psci";numa-node-id = <0>;};cpu7: cpu@13 {device_type = "cpu";compatible = "arm,armv8";reg = <0x0 0x301>;enable-method = "psci";numa-node-id = <0>;};};pcie-controller@40000000 {
pcie@...
compatible = "pci-host-ecam-generic";device_type = "pci";#address-cells = <3>;#size-cells = <2>;reg = <0x0 0x40000000 0x0 0x10000000>;bus-range = <0x0 0xff>;ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>,<0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>,<0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>;};sysclk_48mhz: clk48mhz {compatible = "fixed-clock";#clock-cells = <0x0>;clock-frequency = <48000000>;clock-output-names = "sysclk_48mhz";};uart0: uart@28001000 {
serial@...
This should be under a bus (e.g. simple-bus) node.
compatible = "arm,pl011";reg = <0x0 0x28001000 0x0 0x1000>;clocks = <&sysclk_48mhz>;};+};