Hi Stephen,
On 17 October 2016 at 15:35, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. These dummy implementations are moved into C code, since there's no need to implement them in assembly.
Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/cpu/armv8/cache.S | 6 ------ arch/arm/cpu/armv8/cache_v8.c | 23 ++++++++++++++++++++--- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 4 ++-- arch/arm/include/asm/system.h | 5 ++++- arch/arm/mach-tegra/tegra186/cache.c | 2 +- 5 files changed, 27 insertions(+), 13 deletions(-)
I think we should have a proper interface for this stuff rather than weak functions. Maybe we need a linker-list approach, or a cache uclass?
Regards, Simon