Am 16.01.19 um 14:07 schrieb Gregory CLEMENT:
On some ocelots platform a workaround is needed in order to be able to reset the switch without resetting the DDR.
Signed-off-by: Gregory CLEMENT gregory.clement@bootlin.com
board/mscc/ocelot/ocelot.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c index 0f7a532158..77ebe8ae26 100644 --- a/board/mscc/ocelot/ocelot.c +++ b/board/mscc/ocelot/ocelot.c @@ -10,6 +10,7 @@ #include <environment.h> #include <spi.h> #include <led.h> +#include <wait_bit.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -18,6 +19,31 @@ enum { BOARD_TYPE_PCB123, };
+void mscc_switch_reset(bool enter) +{
- u32 reg, count = 0;
- /* Nasty workaround to avoid GPIO19 (DDR!) being reset */
- mscc_gpio_set_alternate(19, 2);
- debug("applying SwC reset\n");
- writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
- writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
- if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST,
PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false))pr_err("Tiemout while waiting for switch reset\n");- /*
* Reset GPIO19 mode back as regular GPIO, output, high (DDR* not reset) (Order is important)*/- setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
- writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
- mscc_gpio_set_alternate(19, 0);
have you thought about or maybe planned a reset controller driver?
+}
void board_debug_uart_init(void) { /* too early for the pinctrl driver, so configure the UART pins here */