Hi Andrew,
On 15/11/23 21:22, Andrew Davis wrote:
On 11/15/23 4:10 AM, Neha Malcom Francis wrote:
Reduce redundancy in code by using templates to generate the A72 boot binaries (tispl.bin and u-boot.img) as well as R5 boot binary sysfw.itb (for legacy boot following devices J721E and AM65x).
Signed-off-by: Neha Malcom Francis n-francis@ti.com
arch/arm/dts/k3-am625-sk-binman.dtsi | 157 +-------- .../dts/k3-am625-verdin-wifi-dev-binman.dtsi | 155 +------- arch/arm/dts/k3-am62a-sk-binman.dtsi | 158 +-------- arch/arm/dts/k3-am64x-binman.dtsi | 151 +------- arch/arm/dts/k3-am65x-binman.dtsi | 273 +------------- arch/arm/dts/k3-j7200-binman.dtsi | 159 +-------- arch/arm/dts/k3-j721e-binman.dtsi | 332 +----------------- arch/arm/dts/k3-j721s2-binman.dtsi | 157 +-------- 8 files changed, 54 insertions(+), 1488 deletions(-)
1488 deletions, nice!
Minor question, why was `ti-secure` not factored out of `dm` nodes like it was for `atf`/`tee` nodes? Guessing it has to do with not all SoCs needing this blob and signing nothing results in something, which messes up the 0 size check when loading it, but it wasn't clear to me.
Yes that's right! It ends up being non-zero for devices that don't have DM and DM load fails.
Anyway,
Acked-by: Andrew Davis afd@ti.com