This patch adds support for NAND on MPC8610HPCD target. We're using BAT7 and LAW4 entries for 4MB NAND mapping.
MPC8610HPCD has four NAND chips in one package, bases as follows: - 0xe8400000 - 0xe8440000 - 0xe8480000 - 0xe84c0000
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- board/freescale/mpc8610hpcd/law.c | 2 +- include/configs/MPC8610HPCD.h | 37 +++++++++++++++++++++++++++++++------ 2 files changed, 32 insertions(+), 7 deletions(-)
diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c index b4d222d..072a997 100644 --- a/board/freescale/mpc8610hpcd/law.c +++ b/board/freescale/mpc8610hpcd/law.c @@ -33,7 +33,7 @@ struct law_entry law_table[] = { #endif SET_LAW_ENTRY(2, CFG_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), SET_LAW_ENTRY(3, CFG_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), - SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC), /* + NAND */ SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), SET_LAW_ENTRY(6, CFG_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2), SET_LAW_ENTRY(7, CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 15ff0ea..3299942 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -158,10 +158,34 @@
#define CFG_BR1_PRELIM 0xf0001001 /* port size 16bit */ #define CFG_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ -#if 0 /* TODO */ -#define CFG_BR2_PRELIM 0xf0000000 -#define CFG_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ -#endif + +/* + * NAND Flash on Local Bus + */ +#define CFG_NAND_BASE 0xe8400000 +#define CFG_NAND_BR_PRELIM(idx) ((CFG_NAND_BASE + 0x40000 * (idx)) | \ + (2 << BR_DECC_SHIFT) | /* Use HW ECC */ \ + BR_PS_8 | /* Port Size 8 bit */ \ + BR_MS_FCM | /* MSEL FCM */ \ + BR_V) /* valid */ + +#define CFG_NAND_OR_PRELIM (0xFFFF8000 | /* length 32K */ \ + OR_FCM_CSCT | \ + OR_FCM_CST | \ + OR_FCM_CHT | \ + OR_FCM_SCY_1 | \ + OR_FCM_TRLX | \ + OR_FCM_EHTR) + +#define CFG_BR2_PRELIM CFG_NAND_BR_PRELIM(0) +#define CFG_OR2_PRELIM CFG_NAND_OR_PRELIM +#define CFG_BR4_PRELIM CFG_NAND_BR_PRELIM(1) +#define CFG_OR4_PRELIM CFG_NAND_OR_PRELIM +#define CFG_BR5_PRELIM CFG_NAND_BR_PRELIM(2) +#define CFG_OR5_PRELIM CFG_NAND_OR_PRELIM +#define CFG_BR6_PRELIM CFG_NAND_BR_PRELIM(3) +#define CFG_OR6_PRELIM CFG_NAND_OR_PRELIM + #define CFG_BR3_PRELIM 0xe8000801 /* port size 8bit */ #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
@@ -428,12 +452,13 @@ #define CFG_IBAT6U CFG_DBAT6U
/* - * BAT7 4M Cache-inhibited, guarded + * BAT7 8M Cache-inhibited, guarded * 0xe800_0000 4M PIXIS + * 0xe840_0000 4M NAND */ #define CFG_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CFG_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) +#define CFG_DBAT7U (PIXIS_BASE | BATU_BL_8M | BATU_VS | BATU_VP) #define CFG_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT7U CFG_DBAT7U