Hi Tom, On Wednesday 21 August 2013 09:52 AM, Sricharan R wrote:
Hi Tom,
On Wednesday 21 August 2013 01:08 AM, Tom Rini wrote:
On Tue, Aug 20, 2013 at 06:47:36PM +0530, Sricharan R wrote:
Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using software leveling. This was done since hardware leveling was not working. Now that the right sequence to do hw leveling is identified, use it. This is required for EMIF clockdomain to idle and come back during lowpower usecases.
[snip]
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
OK, so this reminds me, should we be printing out something more now then, when we're calculating timings, rather than using precalculated ones? Or is that a different issue I'm thinking of?
This is not something to do with precalculated timings or auto config. This patch is specific only to DDR3 memory and EMIF supports auto leveling feature for DDR3. This feature was disabled for DRA7 till now, but this patch enables that.
I want to add one more change in patch. So will send V2 for this.
Regards, Sricharan