Add initial clock driver for Allwinner A10/A20.
- Implement USB ahb and USB clocks via ccu_clk_map descriptor for A10/A20, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset_map descriptor for A10/A20, so it can accessed in common reset deassert and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/Kconfig | 7 ++++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_a10.c | 77 +++++++++++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100644 drivers/clk/sunxi/clk_a10.c
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index c3713bbac2..fbbf94ef55 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -9,6 +9,13 @@ config CLK_SUNXI
if CLK_SUNXI
+config CLK_SUN4I_A10 + bool "Clock driver for Allwinner A10/A20" + default MACH_SUN4I || MACH_SUN7I + help + This enables common clock driver support for platforms based + on Allwinner A10/A20 SoC. + config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index dec49f27a1..bba830922f 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -6,5 +6,6 @@
obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
+obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c new file mode 100644 index 0000000000..7492e1367a --- /dev/null +++ b/drivers/clk/sunxi/clk_a10.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/arch/ccu.h> +#include <dt-bindings/clock/sun4i-a10-ccu.h> +#include <dt-bindings/reset/sun4i-a10-ccu.h> + +static struct ccu_clk_map a10_clks[] = { + [CLK_AHB_OTG] = { 0x060, BIT(0), NULL }, + [CLK_AHB_EHCI0] = { 0x060, BIT(1), NULL }, + [CLK_AHB_OHCI0] = { 0x060, BIT(2), NULL }, + [CLK_AHB_EHCI1] = { 0x060, BIT(3), NULL }, + [CLK_AHB_OHCI1] = { 0x060, BIT(4), NULL }, + + [CLK_USB_OHCI0] = { 0x0cc, BIT(6), NULL }, + [CLK_USB_OHCI1] = { 0x0cc, BIT(7), NULL }, + [CLK_USB_PHY] = { 0x0cc, BIT(8), NULL }, +}; + +static struct ccu_reset_map a10_resets[] = { + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, + [RST_USB_PHY1] = { 0x0cc, BIT(1) }, + [RST_USB_PHY2] = { 0x0cc, BIT(2) }, +}; + +static const struct ccu_desc sun4i_a10_ccu_desc = { + .clks = a10_clks, + .num_clks = ARRAY_SIZE(a10_clks), + + .resets = a10_resets, + .num_resets = ARRAY_SIZE(a10_resets), +}; + +static int a10_clk_probe(struct udevice *dev) +{ + struct sunxi_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENOMEM; + + priv->desc = (const struct ccu_desc *)dev_get_driver_data(dev); + if (!priv->desc) + return -EINVAL; + + return 0; +} + +static int a10_clk_bind(struct udevice *dev) +{ + return sunxi_reset_bind(dev, 22); +} + +static const struct udevice_id a10_clk_ids[] = { + { .compatible = "allwinner,sun4i-a10-ccu", + .data = (ulong)&sun4i_a10_ccu_desc }, + { .compatible = "allwinner,sun7i-a20-ccu", + .data = (ulong)&sun4i_a10_ccu_desc }, + { } +}; + +U_BOOT_DRIVER(clk_sun4i_a10) = { + .name = "sun4i_a10_ccu", + .id = UCLASS_CLK, + .of_match = a10_clk_ids, + .priv_auto_alloc_size = sizeof(struct sunxi_clk_priv), + .ops = &sunxi_clk_ops, + .probe = a10_clk_probe, + .bind = a10_clk_bind, +};