V1: https://patchwork.ozlabs.org/project/uboot/patch/20240220143603.22091-1-jit.... V2: Fixed Git auto-merge causing misalignment of code and insert/delete V3: Added 240G FPGA DDR region V4: Update defined to is_enabled
Jit Loon Lim (1): arch: arm: Agilex5 enablement
arch/arm/Kconfig | 4 +- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 71 ++ arch/arm/dts/socfpga_agilex5.dtsi | 575 ++++++++++++++ .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 133 ++++ arch/arm/dts/socfpga_agilex5_socdk.dts | 163 ++++ arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 38 +- arch/arm/mach-socfpga/Kconfig | 19 +- arch/arm/mach-socfpga/Makefile | 14 +- arch/arm/mach-socfpga/board.c | 56 +- arch/arm/mach-socfpga/clock_manager_agilex5.c | 89 +++ .../include/mach/base_addr_soc64.h | 38 +- .../mach-socfpga/include/mach/clock_manager.h | 4 +- .../include/mach/clock_manager_agilex5.h | 12 + .../mach-socfpga/include/mach/handoff_soc64.h | 31 +- .../mach-socfpga/include/mach/mailbox_s10.h | 1 + arch/arm/mach-socfpga/mmu-arm64_s10.c | 59 +- board/intel/agilex5-socdk/MAINTAINERS | 8 + configs/socfpga_agilex5_defconfig | 116 +++ drivers/clk/altera/Makefile | 1 + drivers/clk/altera/clk-agilex5.c | 743 ++++++++++++++++++ drivers/clk/altera/clk-agilex5.h | 284 +++++++ include/configs/socfpga_agilex5_socdk.h | 12 + include/configs/socfpga_soc64_common.h | 143 +++- include/dt-bindings/clock/agilex5-clock.h | 71 ++ include/dt-bindings/reset/altr,rst-mgr-agx5.h | 80 ++ 26 files changed, 2730 insertions(+), 36 deletions(-) create mode 100644 arch/arm/dts/socfpga_agilex5-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk.dts create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex5.c create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h create mode 100644 board/intel/agilex5-socdk/MAINTAINERS create mode 100644 configs/socfpga_agilex5_defconfig create mode 100644 drivers/clk/altera/clk-agilex5.c create mode 100644 drivers/clk/altera/clk-agilex5.h create mode 100644 include/configs/socfpga_agilex5_socdk.h create mode 100644 include/dt-bindings/clock/agilex5-clock.h create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agx5.h