The socfpga arch uses a different value for the indaddrtrig reg than the ahbbase address. Adopting the cdns,trigger-address DT bindings from the Linux kernel allows the trigger-address to be set correctly on the socfpga arch.
Tested on Terasic SoCKit dev board (Altera Cyclone V)
Signed-off-by: Jason A. Rush jason.rush@gd-ms.com --- drivers/spi/cadence_qspi.c | 2 ++ drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 4 ++-- 3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 9a6e41f330..b7bed4d4fc 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -297,6 +297,8 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->regbase = (void *)data[0]; plat->ahbbase = (void *)data[2]; plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128); + plat->trigger_address = fdtdec_get_uint(blob, node, + "cdns,trigger-address", 0);
/* All other paramters are embedded in the child node */ subnode = fdt_first_subnode(blob, node); diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index d1927a4003..20fc7a7d9d 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -26,6 +26,7 @@ struct cadence_spi_platdata { u32 tchsh_ns; u32 tslch_ns; u32 sram_size; + u32 trigger_address; };
struct cadence_spi_priv { diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index e02f2217f4..e4ad84c9b1 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -560,7 +560,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, addr_bytes = cmdlen - 1;
/* Setup the indirect trigger address */ - writel((u32)plat->ahbbase, + writel(plat->trigger_address, plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */ @@ -710,7 +710,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, return -EINVAL; } /* Setup the indirect trigger address */ - writel((u32)plat->ahbbase, + writel(plat->trigger_address, plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */