Subject: [PATCH] p1020rdb-pd: platform support
From: Zhang Haijun-B42677 <[email-masked]>
To: Fleming Andy-AFLEMING <[email-masked]>
Cc: "[email-masked]" <[email-masked]>, Zhang Haijun-B42677 <[email-masked]>, Huang Changming-R66093 <[email-masked]>, Wood Scott-B07421 <[email-masked]>, sun york-R58495 <[email-masked]>
Date: Thu, 27 Jun 2013 07:44:02 +0000

From: "Haijun.Zhang" <[email-masked]>

Signed-off-by: Jerry Huang <[email-masked]>
Signed-off-by: Haijun Zhang <[email-masked]>
CC: Scott Wood <[email-masked]>
CC: Sun Yusong-R58495 <[email-masked]>
---
 board/freescale/p1_p2_rdb_pc/ddr.c |  2 +-
 board/freescale/p1_p2_rdb_pc/tlb.c |  2 +-
 boards.cfg                         |  4 ++++
 include/configs/p1_p2_rdb_pc.h     | 48 ++++++++++++++++++++++++++++++++++++--
 4 files changed, 52 insertions(+), 4 deletions(-)

diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 9355536..262fd36 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -80,7 +80,7 @@ dimm_params_t ddr_raw_timing = {
        .refresh_rate_ps = 7800000,
        .tFAW_ps = 30000,
 };
-#elif defined(CONFIG_P1020MBG)
+#elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
 /* Micron MT41J512M8_187E */
 dimm_params_t ddr_raw_timing = {
        .n_ranks = 2,
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 3e4dffd..e19002f 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -110,7 +110,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
                        0, 8, BOOKE_PAGESZ_1G, 1),

-#ifdef CONFIG_P1020MBG
+#if defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)
        /* 2G DDR on P1020MBG, map the second 1G */
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
                        CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
diff --git a/boards.cfg b/boards.cfg
index 35f38f3..aefff92 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -768,6 +768,10 @@ P1020RDB-PC_SDCARD           powerpc     mpc85xx     p1_p2_rdb_pc        freesca
 P1020RDB-PC_SPIFLASH         powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020RDB,SPIFLASH
 P1020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1020RDB,SDCARD
 P1020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1020RDB,SPIFLASH
+P1020RDB-PD                  powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020RDB_PD
+P1020RDB-PD_NAND             powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020RDB_PD,NAND
+P1020RDB-PD_SDCARD           powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020RDB_PD,SDCARD
+P1020RDB-PD_SPIFLASH         powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020RDB_PD,SPIFLASH
 P1020UTM-PC                  powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020UTM
 P1020UTM-PC_36BIT            powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020UTM,36BIT
 P1020UTM-PC_36BIT_SDCARD     powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1020UTM,36BIT,SDCARD
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 964bfcd..36aad8c 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -66,6 +66,35 @@
 #define CONFIG_SYS_L2_SIZE     (256 << 10)
 #endif

+/*
+ * P1020RDB-PD board has user selectable switches for evaluating different
+ * frequency and boot options for the P1020 device. The table that
+ * follow describe the available options. The front six binary number was in
+ * accordance with SW3[1:6].
+ * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
+ * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
+ * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
+ * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
+ * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
+ * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
+ * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
+ */
+#if defined(CONFIG_P1020RDB_PD)
+#define CONFIG_BOARDNAME "P1020RDB-PD"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_P1020
+#define CONFIG_SPI_FLASH
+#define CONFIG_VSC7385_ENET
+#define CONFIG_SLIC
+#define __SW_BOOT_MASK         0x03
+#define __SW_BOOT_NOR          0x64
+#define __SW_BOOT_SPI          0x34
+#define __SW_BOOT_SD           0x24
+#define __SW_BOOT_NAND         0x44
+#define __SW_BOOT_PCIE         0x74
+#define CONFIG_SYS_L2_SIZE     (256 << 10)
+#endif
+
 #if defined(CONFIG_P1021RDB)
 #define CONFIG_BOARDNAME "P1021RDB-PC"
 #define CONFIG_NAND_FSL_ELBC
@@ -274,7 +303,7 @@
 #define SPD_EEPROM_ADDRESS 0x52
 #undef CONFIG_FSL_DDR_INTERACTIVE

-#ifdef CONFIG_P1020MBG
+#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
 #define CONFIG_SYS_SDRAM_SIZE_LAW      LAW_SIZE_2G
 #define CONFIG_CHIP_SELECTS_PER_CTRL   2
 #else
@@ -345,7 +374,7 @@
 /*
  * Local Bus Definitions
  */
-#if defined(CONFIG_P1020MBG)
+#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
 #define CONFIG_SYS_MAX_FLASH_SECT      512     /* 64M */
 #define CONFIG_SYS_FLASH_BASE          0xec000000
 #elif defined(CONFIG_P1020UTM)
@@ -396,13 +425,27 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_CMD_NAND
+#if defined(CONFIG_P1020RDB_PD)
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
+#else
 #define CONFIG_SYS_NAND_BLOCK_SIZE     (16 * 1024)
+#endif

 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
        | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
        | BR_PS_8       /* Port Size = 8 bit */ \
        | BR_MS_FCM     /* MSEL = FCM */ \
        | BR_V) /* valid */
+#if defined(CONFIG_P1020RDB_PD)
+#define CONFIG_SYS_NAND_OR_PRELIM      (OR_AM_32KB \
+       | OR_FCM_PGS    /* Large Page*/ \
+       | OR_FCM_CSCT \
+       | OR_FCM_CST \
+       | OR_FCM_CHT \
+       | OR_FCM_SCY_1 \
+       | OR_FCM_TRLX \
+       | OR_FCM_EHTR)
+#else
 #define CONFIG_SYS_NAND_OR_PRELIM      (OR_AM_32KB     /* small page */ \
        | OR_FCM_CSCT \
        | OR_FCM_CST \
@@ -410,6 +453,7 @@
        | OR_FCM_SCY_1 \
        | OR_FCM_TRLX \
        | OR_FCM_EHTR)
+#endif
 #endif /* CONFIG_NAND_FSL_ELBC */

 #define CONFIG_BOARD_EARLY_INIT_R      /* call board_early_init_r function */
--
1.8.0