ARM926EJS core with MX31 peripherals.
Signed-off-by: John Rigby jcrigby@gmail.com Earlier Version Signed-off-by: Wolfgang Denk wd@denx.de CC: Fred Fan fanyefeng@gmail.com CC: Tom Tom.Rix@windriver.com --- cpu/arm926ejs/mx25/Makefile | 46 ++++ cpu/arm926ejs/mx25/generic.c | 263 +++++++++++++++++++ cpu/arm926ejs/mx25/reset.c | 56 ++++ cpu/arm926ejs/mx25/timer.c | 187 +++++++++++++ drivers/serial/serial_mxc.c | 10 +- include/asm-arm/arch-mx25/clock.h | 35 +++ include/asm-arm/arch-mx25/imx-regs.h | 330 +++++++++++++++++++++++ include/asm-arm/arch-mx25/imx25-pinmux.h | 421 ++++++++++++++++++++++++++++++ 8 files changed, 1343 insertions(+), 5 deletions(-) create mode 100644 cpu/arm926ejs/mx25/Makefile create mode 100644 cpu/arm926ejs/mx25/generic.c create mode 100644 cpu/arm926ejs/mx25/reset.c create mode 100644 cpu/arm926ejs/mx25/timer.c create mode 100644 include/asm-arm/arch-mx25/clock.h create mode 100644 include/asm-arm/arch-mx25/imx-regs.h create mode 100644 include/asm-arm/arch-mx25/imx25-pinmux.h
diff --git a/cpu/arm926ejs/mx25/Makefile b/cpu/arm926ejs/mx25/Makefile new file mode 100644 index 0000000..55c1e89 --- /dev/null +++ b/cpu/arm926ejs/mx25/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = generic.o timer.o +MX27OBJS = reset.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS += $(addprefix $(SRCTREE)/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(MX27OBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/mx25/generic.c b/cpu/arm926ejs/mx25/generic.c new file mode 100644 index 0000000..694841d --- /dev/null +++ b/cpu/arm926ejs/mx25/generic.c @@ -0,0 +1,263 @@ +/* + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby jrigby@gmail.com + * + * Based on mx27/generic.c: + * Copyright (c) 2008 Eric Jarrige eric.jarrige@armadeus.org + * Copyright (c) 2009 Ilya Yanok yanok@emcraft.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <div64.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/imx25-pinmux.h> +#ifdef CONFIG_MXC_MMC +#include <asm/arch/mxcmmc.h> +#endif + +/* + * get the system pll clock in Hz + * + * mfi + mfn / (mfd +1) + * f = 2 * f_ref * -------------------- + * pd + 1 + */ +static unsigned int imx_decode_pll (unsigned int pll, unsigned int f_ref) +{ + unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT) + & CCM_PLL_MFI_MASK; + unsigned int mfn = (pll >> CCM_PLL_MFN_SHIFT) + & CCM_PLL_MFN_MASK; + unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT) + & CCM_PLL_MFD_MASK; + unsigned int pd = (pll >> CCM_PLL_PD_SHIFT) + & CCM_PLL_PD_MASK; + + mfi = mfi <= 5 ? 5 : mfi; + + return lldiv (2 * (u64) f_ref * (mfi * (mfd + 1) + mfn), + (mfd + 1) * (pd + 1)); +} + +static ulong imx_get_mpllclk (void) +{ + struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; + ulong fref = 24000000; + + return imx_decode_pll (readl (&ccm->mpctl), fref); +} + +ulong imx_get_armclk (void) +{ + struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; + ulong cctl = readl (&ccm->cctl); + ulong fref = imx_get_mpllclk (); + ulong div; + + if (cctl & CCM_CCTL_ARM_SRC) + fref = lldiv ((fref * 3), 4); + + div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT) + & CCM_CCTL_ARM_DIV_MASK) + 1; + + return lldiv (fref, div); +} + +ulong imx_get_ahbclk (void) +{ + struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; + ulong cctl = readl (&ccm->cctl); + ulong fref = imx_get_armclk (); + ulong div; + + div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT) + & CCM_CCTL_AHB_DIV_MASK) + 1; + + return lldiv (fref, div); +} + +ulong imx_get_perclk (int clk) +{ + struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; + ulong fref = imx_get_ahbclk (); + ulong div; + + div = readl (&ccm->pcdr[CCM_PERCLK_REG (clk)]); + div = ((div >> CCM_PERCLK_SHIFT (clk)) & CCM_PERCLK_MASK) + 1; + + return lldiv (fref, div); +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo (void) +{ + char buf[32]; + + printf ("CPU: Freescale i.MX25 at %s MHz\n\n", + strmhz (buf, imx_get_mpllclk ())); + return 0; +} +#endif + +int cpu_eth_init (bd_t * bis) +{ +#if defined(CONFIG_FEC_MXC) + struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; + ulong val; + + val = readl (&ccm->cgr0); + val |= (1 << 23); + writel (val, &ccm->cgr0); + return fecmxc_initialize (bis); +#else + return 0; +#endif +} + +/* + * Initializes on-chip MMC controllers. + * to override, implement board_mmc_init() + */ +int cpu_mmc_init (bd_t * bis) +{ +#ifdef CONFIG_MXC_MMC + return mxc_mmc_init (bis); +#else + return 0; +#endif +} + +#ifdef CONFIG_MXC_UART +void mx25_uart_init_pins (void) +{ + struct iomuxc_mux_ctl *muxctl; + struct iomuxc_pad_ctl *padctl; + u32 inpadctl; + u32 outpadctl; + u32 muxmode0; + + muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; + padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; + muxmode0 = MX25_PIN_MUX_MODE (0); + /* + * set up input pins with hysteresis and 100K pull-ups + */ + inpadctl = MX25_PIN_PAD_CTL_HYS + | MX25_PIN_PAD_CTL_PKE + | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU; + + /* + * set up output pins with 100K pull-downs + * FIXME: need to revisit this + * PUE is ignored if PKE is not set + * so the right value here is likely + * 0x0 for no pull up/down + * or + * 0xc0 for 100k pull down + */ + outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; + + /* UART1 */ + /* rxd */ + writel (muxmode0, &muxctl->pad_uart1_rxd); + writel (inpadctl, &padctl->pad_uart1_rxd); + + /* txd */ + writel (muxmode0, &muxctl->pad_uart1_txd); + writel (outpadctl, &padctl->pad_uart1_txd); + + /* rts */ + writel (muxmode0, &muxctl->pad_uart1_rts); + writel (outpadctl, &padctl->pad_uart1_rts); + + /* cts */ + writel (muxmode0, &muxctl->pad_uart1_cts); + writel (inpadctl, &padctl->pad_uart1_cts); +} +#endif /* CONFIG_MXC_UART */ + +#ifdef CONFIG_FEC_MXC +void mx25_fec_init_pins (void) +{ + struct iomuxc_mux_ctl *muxctl; + struct iomuxc_pad_ctl *padctl; + u32 inpadctl_100kpd; + u32 inpadctl_22kpu; + u32 outpadctl; + u32 muxmode0; + + muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; + padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; + muxmode0 = MX25_PIN_MUX_MODE (0); + inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS + | MX25_PIN_PAD_CTL_PKE + | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; + inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS + | MX25_PIN_PAD_CTL_PKE + | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU; + /* + * set up output pins with 100K pull-downs + * FIXME: need to revisit this + * PUE is ignored if PKE is not set + * so the right value here is likely + * 0x0 for no pull + * or + * 0xc0 for 100k pull down + */ + outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD; + + /* FEC_TX_CLK */ + writel (muxmode0, &muxctl->pad_fec_tx_clk); + writel (inpadctl_100kpd, &padctl->pad_fec_tx_clk); + + /* FEC_RX_DV */ + writel (muxmode0, &muxctl->pad_fec_rx_dv); + writel (inpadctl_100kpd, &padctl->pad_fec_rx_dv); + + /* FEC_RDATA0 */ + writel (muxmode0, &muxctl->pad_fec_rdata0); + writel (inpadctl_100kpd, &padctl->pad_fec_rdata0); + + /* FEC_TDATA0 */ + writel (muxmode0, &muxctl->pad_fec_tdata0); + writel (outpadctl, &padctl->pad_fec_tdata0); + + /* FEC_TX_EN */ + writel (muxmode0, &muxctl->pad_fec_tx_en); + writel (outpadctl, &padctl->pad_fec_tx_en); + + /* FEC_MDC */ + writel (muxmode0, &muxctl->pad_fec_mdc); + writel (outpadctl, &padctl->pad_fec_mdc); + + /* FEC_MDIO */ + writel (muxmode0, &muxctl->pad_fec_mdio); + writel (inpadctl_22kpu, &padctl->pad_fec_mdio); + + /* FEC_RDATA1 */ + writel (muxmode0, &muxctl->pad_fec_rdata1); + writel (inpadctl_100kpd, &padctl->pad_fec_rdata1); + + /* FEC_TDATA1 */ + writel (muxmode0, &muxctl->pad_fec_tdata1); + writel (outpadctl, &padctl->pad_fec_tdata1); + +} +#endif /* CONFIG_FEC_MXC */ diff --git a/cpu/arm926ejs/mx25/reset.c b/cpu/arm926ejs/mx25/reset.c new file mode 100644 index 0000000..1e33150 --- /dev/null +++ b/cpu/arm926ejs/mx25/reset.c @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke azu@sysgo.de + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, gj@denx.de + * + * (C) Copyright 2009 + * Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> + +/* + * Reset the cpu by setting up the watchdog timer and let it time out + */ +void reset_cpu (ulong ignored) +{ + struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; + /* Disable watchdog and set Time-Out field to 0 */ + writel (0x00000000, ®s->wcr); + + /* Write Service Sequence */ + writel (0x00005555, ®s->wsr); + writel (0x0000AAAA, ®s->wsr); + + /* Enable watchdog */ + writel (WCR_WDE, ®s->wcr); + + while (1) ; +} diff --git a/cpu/arm926ejs/mx25/timer.c b/cpu/arm926ejs/mx25/timer.c new file mode 100644 index 0000000..11d41a8 --- /dev/null +++ b/cpu/arm926ejs/mx25/timer.c @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke azu@sysgo.de + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, gj@denx.de + * + * (C) Copyright 2009 + * Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com + * + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby jrigby@gmail.com + * Add support for MX25 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <div64.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> + +static ulong timestamp; +static ulong lastinc; + +/* + * "time" is measured in 1 / CONFIG_SYS_HZ seconds, + * "tick" is internal timer period + */ +#ifdef CONFIG_MX25_TIMER_HIGH_PRECISION +/* ~0.4% error - measured with stop-watch on 100s boot-delay */ +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, CONFIG_MX25_CLK32); + return tick; +} + +static inline unsigned long long time_to_tick(unsigned long long time) +{ + time *= CONFIG_MX25_CLK32; + do_div(time, CONFIG_SYS_HZ); + return time; +} + +static inline unsigned long long us_to_tick(unsigned long long us) +{ + us = us * CONFIG_MX25_CLK32 + 999999; + do_div(us, 1000000); + return us; +} +#else +/* ~2% error */ +#define TICK_PER_TIME ((CONFIG_MX25_CLK32 + CONFIG_SYS_HZ / 2) / \ + CONFIG_SYS_HZ) +#define US_PER_TICK (1000000 / CONFIG_MX25_CLK32) + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + do_div(tick, TICK_PER_TIME); + return tick; +} + +static inline unsigned long long time_to_tick(unsigned long long time) +{ + return time * TICK_PER_TIME; +} + +static inline unsigned long long us_to_tick(unsigned long long us) +{ + us += US_PER_TICK - 1; + do_div(us, US_PER_TICK); + return us; +} +#endif + +/* nothing really to do with interrupts, just starts up a counter. */ +/* The 32KHz 32-bit timer overruns in 134217 seconds */ +int timer_init(void) +{ + int i; + struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE; + struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; + + /* setup GP Timer 1 */ + writel(GPT_CTRL_SWR, &gpt->ctrl); + + writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1); + + for (i = 0; i < 100; i++) + writel(0, &gpt->ctrl); /* We have no udelay by now */ + writel(0, &gpt->pre); /* prescaler = 1 */ + /* Freerun Mode, 32KHz input */ + writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR, + &gpt->ctrl); + writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl); + + return 0; +} + +void reset_timer_masked(void) +{ + struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE; + /* reset time */ + /* capture current incrementer value time */ + lastinc = readl(&gpt->counter); + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +unsigned long long get_ticks (void) +{ + struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE; + ulong now = readl(&gpt->counter); /* current tick value */ + + if (now >= lastinc) { + /* + * normal mode (non roll) + * move stamp forward with absolut diff ticks + */ + timestamp += (now - lastinc); + } else { + /* we have rollover of incrementer */ + timestamp += (0xFFFFFFFF - lastinc) + now; + } + lastinc = now; + return timestamp; +} + +ulong get_timer_masked (void) +{ + /* + * get_ticks() returns a long long (64 bit), it wraps in + * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in + * 5 * 10^6 days - long enough. + */ + return tick_to_time(get_ticks()); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = time_to_tick(t); +} + +/* delay x useconds AND preserve advance timstamp value */ +void __udelay (unsigned long usec) +{ + unsigned long long tmp; + ulong tmo; + + tmo = us_to_tick(usec); + tmp = get_ticks() + tmo; /* get current timestamp */ + + while (get_ticks() < tmp) /* loop till event */ + /*NOP*/; +} diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 7dcedf6..70c1c1e 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -27,15 +27,15 @@
#define __REG(x) (*((volatile u32 *)(x)))
-#ifdef CONFIG_SYS_MX31_UART1 +#if defined(CONFIG_SYS_MX31_UART1) || defined(CONFIG_SYS_MX25_UART1) #define UART_PHYS 0x43f90000 -#elif defined(CONFIG_SYS_MX31_UART2) +#elif defined(CONFIG_SYS_MX31_UART2) || defined(CONFIG_SYS_MX25_UART2) #define UART_PHYS 0x43f94000 -#elif defined(CONFIG_SYS_MX31_UART3) +#elif defined(CONFIG_SYS_MX31_UART3) || defined(CONFIG_SYS_MX25_UART3) #define UART_PHYS 0x5000c000 -#elif defined(CONFIG_SYS_MX31_UART4) +#elif defined(CONFIG_SYS_MX31_UART4) || defined(CONFIG_SYS_MX25_UART4) #define UART_PHYS 0x43fb0000 -#elif defined(CONFIG_SYS_MX31_UART5) +#elif defined(CONFIG_SYS_MX31_UART5) || defined(CONFIG_SYS_MX25_UART5) #define UART_PHYS 0x43fb4000 #elif defined(CONFIG_SYS_MX27_UART1) #define UART_PHYS 0x1000a000 diff --git a/include/asm-arm/arch-mx25/clock.h b/include/asm-arm/arch-mx25/clock.h new file mode 100644 index 0000000..b0752e7 --- /dev/null +++ b/include/asm-arm/arch-mx25/clock.h @@ -0,0 +1,35 @@ +/* + * + * (c) 2009 Ilya Yanok, Emcraft Systems yanok@emcraft.com + * + * Modified for mx25 by John Rigby jrigby@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +ulong imx_get_perclk(int clk); +ulong imx_get_ahbclk(void); + +#define imx_get_uartclk() imx_get_perclk(15) + + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/include/asm-arm/arch-mx25/imx-regs.h b/include/asm-arm/arch-mx25/imx-regs.h new file mode 100644 index 0000000..23c1471 --- /dev/null +++ b/include/asm-arm/arch-mx25/imx-regs.h @@ -0,0 +1,330 @@ +/* + * Copyright (C) 2009, DENX Software Engineering + * Author: John Rigby <jcrigby@gmail.com + * + * Based on arch-mx31/mx31-regs.h + * Copyright (C) 2009 Ilya Yanok, + * Emcraft Systems yanok@emcraft.com + * and arch-mx27/imx-regs.h + * Copyright (C) 2007 Pengutronix, + * Sascha Hauer s.hauer@pengutronix.de + * Copyright (C) 2009 Ilya Yanok, + * Emcraft Systems yanok@emcraft.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _IMX_REGS_H +#define _IMX_REGS_H + +#ifndef __ASSEMBLY__ +#ifdef CONFIG_FEC_MXC +extern void mx25_fec_init_pins(void); +#endif + +/* Clock Control Module (CCM) registers */ +struct ccm_regs { + u32 mpctl; /* Core PLL Control */ + u32 upctl; /* USB PLL Control */ + u32 cctl; /* Clock Control */ + u32 cgr0; /* Clock Gating Control 0 */ + u32 cgr1; /* Clock Gating Control 1 */ + u32 cgr2; /* Clock Gating Control 2 */ + u32 pcdr[4]; /* PER Clock Dividers */ + u32 rcsr; /* CCM Status */ + u32 crdr; /* CCM Reset and Debug */ + u32 dcvr0; /* DPTC Comparator Value 0 */ + u32 dcvr1; /* DPTC Comparator Value 1 */ + u32 dcvr2; /* DPTC Comparator Value 2 */ + u32 dcvr3; /* DPTC Comparator Value 3 */ + u32 ltr0; /* Load Tracking 0 */ + u32 ltr1; /* Load Tracking 1 */ + u32 ltr2; /* Load Tracking 2 */ + u32 ltr3; /* Load Tracking 3 */ + u32 ltbr0; /* Load Tracking Buffer 0 */ + u32 ltbr1; /* Load Tracking Buffer 1 */ + u32 pcmr0; /* Power Management Control 0 */ + u32 pcmr1; /* Power Management Control 1 */ + u32 pcmr2; /* Power Management Control 2 */ + u32 mcr; /* Miscellaneous Control */ + u32 lpimr0; /* Low Power Interrupt Mask 0 */ + u32 lpimr1; /* Low Power Interrupt Mask 1 */ +}; + +/* Enhanced SDRAM Controller (ESDRAMC) registers */ +struct esdramc_regs { + u32 ctl0; /* control 0 */ + u32 cfg0; /* configuration 0 */ + u32 ctl1; /* control 1 */ + u32 cfg1; /* configuration 1 */ + u32 misc; /* miscellaneous */ + u32 pad[3]; + u32 cdly1; /* Delay Line 1 configuration debug */ + u32 cdly2; /* delay line 2 configuration debug */ + u32 cdly3; /* delay line 3 configuration debug */ + u32 cdly4; /* delay line 4 configuration debug */ + u32 cdly5; /* delay line 5 configuration debug */ + u32 cdlyl; /* delay line cycle length debug */ +}; + +/* GPIO registers */ +struct gpio_regs { + u32 dr; /* data */ + u32 dir; /* direction */ + u32 psr; /* pad satus */ + u32 icr1; /* interrupt config 1 */ + u32 icr2; /* interrupt config 2 */ + u32 imr; /* interrupt mask */ + u32 isr; /* interrupt status */ + u32 edge_sel; /* edge select */ +}; + +/* General Purpose Timer (GPT) registers */ +struct gpt_regs { + u32 ctrl; /* control */ + u32 pre; /* prescaler */ + u32 stat; /* status */ + u32 intr; /* interrupt */ + u32 cmp[3]; /* output compare 1-3 */ + u32 capt[2]; /* input capture 1-2 */ + u32 counter; /* counter */ +}; + +/* Watchdog Timer (WDOG) registers */ +struct wdog_regs { + u32 wcr; /* Control */ + u32 wsr; /* Service */ + u32 wrsr; /* Reset Status */ + u32 wicr; /* Interrupt Control */ + u32 wmcr; /* Misc Control */ +}; + +/* IIM control registers */ +struct iim_regs { + u32 iim_stat; + u32 iim_statm; + u32 iim_err; + u32 iim_emask; + u32 iim_fctl; + u32 iim_ua; + u32 iim_la; + u32 iim_sdat; + u32 iim_prev; + u32 iim_srev; + u32 iim_prog_p; + u32 res1[0x1f5]; + u32 iim_bank_area0[0x20]; + u32 res2[0xe0]; + u32 iim_bank_area1[0x20]; + u32 res3[0xe0]; + u32 iim_bank_area2[0x20]; +}; +#endif + +/* AIPS 1 */ +#define IMX_AIPS1_BASE (0x43F00000) +#define IMX_MAX_BASE (0x43F04000) +#define IMX_CLKCTL_BASE (0x43F08000) +#define IMX_ETB_SLOT4_BASE (0x43F0C000) +#define IMX_ETB_SLOT5_BASE (0x43F10000) +#define IMX_ECT_CTIO_BASE (0x43F18000) +#define IMX_I2C_BASE (0x43F80000) +#define IMX_I2C3_BASE (0x43F84000) +#define IMX_CAN1_BASE (0x43F88000) +#define IMX_CAN2_BASE (0x43F8C000) +#define IMX_UART1_BASE (0x43F90000) +#define IMX_UART2_BASE (0x43F94000) +#define IMX_I2C2_BASE (0x43F98000) +#define IMX_OWIRE_BASE (0x43F9C000) +#define IMX_CSPI1_BASE (0x43FA4000) +#define IMX_KPP_BASE (0x43FA8000) +#define IMX_IOPADMUX_BASE (0x43FAC000) +#define IMX_IOPADCTL_BASE (0x43FAC22C) +#define IMX_IOPADGRPCTL_BASE (0x43FAC418) +#define IMX_IOPADINPUTSEL_BASE (0x43FAC460) +#define IMX_AUDMUX_BASE (0x43FB0000) +#define IMX_ECT_IP1_BASE (0x43FB8000) +#define IMX_ECT_IP2_BASE (0x43FBC000) + +/* SPBA */ +#define IMX_SPBA_BASE (0x50000000) +#define IMX_CSPI3_BASE (0x50004000) +#define IMX_UART4_BASE (0x50008000) +#define IMX_UART3_BASE (0x5000C000) +#define IMX_CSPI2_BASE (0x50010000) +#define IMX_SSI2_BASE (0x50014000) +#define IMX_ESAI_BASE (0x50018000) +#define IMX_ATA_DMA_BASE (0x50020000) +#define IMX_SIM1_BASE (0x50024000) +#define IMX_SIM2_BASE (0x50028000) +#define IMX_UART5_BASE (0x5002C000) +#define IMX_TSC_BASE (0x50030000) +#define IMX_SSI1_BASE (0x50034000) +#define IMX_FEC_BASE (0x50038000) +#define IMX_SPBA_CTRL_BASE (0x5003C000) + +/* AIPS 2 */ +#define IMX_AIPS2_BASE (0x53F00000) +#define IMX_CCM_BASE (0x53F80000) +#define IMX_GPT4_BASE (0x53F84000) +#define IMX_GPT3_BASE (0x53F88000) +#define IMX_GPT2_BASE (0x53F8C000) +#define IMX_GPT1_BASE (0x53F90000) +#define IMX_EPIT1_BASE (0x53F94000) +#define IMX_EPIT2_BASE (0x53F98000) +#define IMX_GPIO4_BASE (0x53F9C000) +#define IMX_PWM2_BASE (0x53FA0000) +#define IMX_GPIO3_BASE (0x53FA4000) +#define IMX_PWM3_BASE (0x53FA8000) +#define IMX_SCC_BASE (0x53FAC000) +#define IMX_SCM_BASE (0x53FAE000) +#define IMX_SMN_BASE (0x53FAF000) +#define IMX_RNGD_BASE (0x53FB0000) +#define IMX_MMC_SDHC1_BASE (0x53FB4000) +#define IMX_MMC_SDHC2_BASE (0x53FB8000) +#define IMX_LCDC_BASE (0x53FBC000) +#define IMX_SLCDC_BASE (0x53FC0000) +#define IMX_PWM4_BASE (0x53FC8000) +#define IMX_GPIO1_BASE (0x53FCC000) +#define IMX_GPIO2_BASE (0x53FD0000) +#define IMX_SDMA_BASE (0x53FD4000) +#define IMX_WDT_BASE (0x53FDC000) +#define IMX_PWM1_BASE (0x53FE0000) +#define IMX_RTIC_BASE (0x53FEC000) +#define IMX_IIM_BASE (0x53FF0000) +#define IMX_USB_BASE (0x53FF4000) +#define IMX_CSI_BASE (0x53FF8000) +#define IMX_DRYICE_BASE (0x53FFC000) + +#define IMX_ARM926_ROMPATCH (0x60000000) +#define IMX_ARM926_ASIC (0x68000000) + +/* 128K Internal Static RAM */ +#define IMX_RAM_BASE (0x78000000) + +/* SDRAM BANKS */ +#define IMX_SDRAM_BANK0_BASE (0x80000000) +#define IMX_SDRAM_BANK1_BASE (0x90000000) + +#define IMX_WEIM_CS0 (0xA0000000) +#define IMX_WEIM_CS1 (0xA8000000) +#define IMX_WEIM_CS2 (0xB0000000) +#define IMX_WEIM_CS3 (0xB2000000) +#define IMX_WEIM_CS4 (0xB4000000) +#define IMX_ESDRAMC_BASE (0xB8001000) +#define IMX_WEIM_CTRL_BASE (0xB8002000) +#define IMX_M3IF_CTRL_BASE (0xB8003000) +#define IMX_EMI_CTRL_BASE (0xB8004000) + +/* NAND Flash Controller */ +#define IMX_NFC_BASE (0xBB000000) +#define NFC_BASE_ADDR IMX_NFC_BASE + +/* CCM bitfields */ +#define CCM_PLL_MFI_SHIFT 10 +#define CCM_PLL_MFI_MASK 0xf +#define CCM_PLL_MFN_SHIFT 0 +#define CCM_PLL_MFN_MASK 0x3ff +#define CCM_PLL_MFD_SHIFT 16 +#define CCM_PLL_MFD_MASK 0x3ff +#define CCM_PLL_PD_SHIFT 26 +#define CCM_PLL_PD_MASK 0xf +#define CCM_CCTL_ARM_DIV_SHIFT 30 +#define CCM_CCTL_ARM_DIV_MASK 3 +#define CCM_CCTL_AHB_DIV_SHIFT 28 +#define CCM_CCTL_AHB_DIV_MASK 3 +#define CCM_CCTL_ARM_SRC (1 << 14) +#define CCM_CGR1_GPT1 (1 << 19) +#define CCM_PERCLK_REG(clk) (clk / 4) +#define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4)) +#define CCM_PERCLK_MASK 0x3f +#define CCM_RCSR_NF_16BIT_SEL (1 << 14) +#define CCM_RCSR_NF_PS(v) ((v >> 26) & 3) + + +#ifndef __ASSEMBLY__ +#include <asm/io.h> + +static inline long mxc_get_nfc_info(void) +{ + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + return readl(&ccm->rcsr); +} +#define IMX_NFC_IS_16BIT(rcsr) (rcsr & CCM_RCSR_NF_16BIT_SEL) +#define IMX_NFC_IS_2KPAGE(rcsr) (CCM_RCSR_NF_PS(rcsr) == 1) +#endif + +/* ESDRAM Controller register bitfields */ +#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) +#define ESDCTL_BL (1 << 7) +#define ESDCTL_FP (1 << 8) +#define ESDCTL_PWDT(x) (((x) & 3) << 10) +#define ESDCTL_SREFR(x) (((x) & 7) << 13) +#define ESDCTL_DSIZ_16_UPPER (0 << 16) +#define ESDCTL_DSIZ_16_LOWER (1 << 16) +#define ESDCTL_DSIZ_32 (2 << 16) +#define ESDCTL_COL8 (0 << 20) +#define ESDCTL_COL9 (1 << 20) +#define ESDCTL_COL10 (2 << 20) +#define ESDCTL_ROW11 (0 << 24) +#define ESDCTL_ROW12 (1 << 24) +#define ESDCTL_ROW13 (2 << 24) +#define ESDCTL_ROW14 (3 << 24) +#define ESDCTL_ROW15 (4 << 24) +#define ESDCTL_SP (1 << 27) +#define ESDCTL_SMODE_NORMAL (0 << 28) +#define ESDCTL_SMODE_PRECHARGE (1 << 28) +#define ESDCTL_SMODE_AUTO_REF (2 << 28) +#define ESDCTL_SMODE_LOAD_MODE (3 << 28) +#define ESDCTL_SMODE_MAN_REF (4 << 28) +#define ESDCTL_SDE (1 << 31) + +#define ESDCFG_TRC(x) (((x) & 0xf) << 0) +#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) +#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) +#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) +#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) +#define ESDCFG_TWR (1 << 15) +#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) +#define ESDCFG_TRP(x) (((x) & 0x3) << 18) +#define ESDCFG_TWTR (1 << 20) +#define ESDCFG_TXP(x) (((x) & 0x3) << 21) + +#define ESDMISC_RST (1 << 1) +#define ESDMISC_MDDREN (1 << 2) +#define ESDMISC_MDDR_DL_RST (1 << 3) +#define ESDMISC_MDDR_MDIS (1 << 4) +#define ESDMISC_LHD (1 << 5) +#define ESDMISC_MA10_SHARE (1 << 6) +#define ESDMISC_SDRAM_RDY (1 << 31) + +/* GPT bits */ +#define GPT_CTRL_SWR (1 << 15) /* Software reset */ +#define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */ +#define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */ +#define GPT_CTRL_TEN 1 /* Timer enable */ + +/* WDOG enable */ +#define WCR_WDE 0x04 + +/* FUSE bank offsets */ +#define IIM0_MAC 0x1a + +#endif /* _IMX_REGS_H */ diff --git a/include/asm-arm/arch-mx25/imx25-pinmux.h b/include/asm-arm/arch-mx25/imx25-pinmux.h new file mode 100644 index 0000000..a4c658b --- /dev/null +++ b/include/asm-arm/arch-mx25/imx25-pinmux.h @@ -0,0 +1,421 @@ +/* + * iopin settings are controlled by four different sets of registers + * iopad mux control + * individual iopad setup (voltage select, pull/keep, drive strength ...) + * group iopad setup (same as above but for groups of signals) + * input select when multiple inputs are possible + */ + +/* + * software pad mux control + */ +/* SW Input On (Loopback) */ +#define MX25_PIN_MUX_SION (1 << 4) +/* MUX Mode (0-7) */ +#define MX25_PIN_MUX_MODE(mode) ((mode & 0x7) << 0) +struct iomuxc_mux_ctl { + u32 gpr1; + u32 observe_int_mux; + u32 pad_a10; + u32 pad_a13; + u32 pad_a14; + u32 pad_a15; + u32 pad_a16; + u32 pad_a17; + u32 pad_a18; + u32 pad_a19; + u32 pad_a20; + u32 pad_a21; + u32 pad_a22; + u32 pad_a23; + u32 pad_a24; + u32 pad_a25; + u32 pad_eb0; + u32 pad_eb1; + u32 pad_oe; + u32 pad_cs0; + u32 pad_cs1; + u32 pad_cs4; + u32 pad_cs5; + u32 pad_nf_ce0; + u32 pad_ecb; + u32 pad_lba; + u32 pad_bclk; + u32 pad_rw; + u32 pad_nfwe_b; + u32 pad_nfre_b; + u32 pad_nfale; + u32 pad_nfcle; + u32 pad_nfwp_b; + u32 pad_nfrb; + u32 pad_d15; + u32 pad_d14; + u32 pad_d13; + u32 pad_d12; + u32 pad_d11; + u32 pad_d10; + u32 pad_d9; + u32 pad_d8; + u32 pad_d7; + u32 pad_d6; + u32 pad_d5; + u32 pad_d4; + u32 pad_d3; + u32 pad_d2; + u32 pad_d1; + u32 pad_d0; + u32 pad_ld0; + u32 pad_ld1; + u32 pad_ld2; + u32 pad_ld3; + u32 pad_ld4; + u32 pad_ld5; + u32 pad_ld6; + u32 pad_ld7; + u32 pad_ld8; + u32 pad_ld9; + u32 pad_ld10; + u32 pad_ld11; + u32 pad_ld12; + u32 pad_ld13; + u32 pad_ld14; + u32 pad_ld15; + u32 pad_hsync; + u32 pad_vsync; + u32 pad_lsclk; + u32 pad_oe_acd; + u32 pad_contrast; + u32 pad_pwm; + u32 pad_csi_d2; + u32 pad_csi_d3; + u32 pad_csi_d4; + u32 pad_csi_d5; + u32 pad_csi_d6; + u32 pad_csi_d7; + u32 pad_csi_d8; + u32 pad_csi_d9; + u32 pad_csi_mclk; + u32 pad_csi_vsync; + u32 pad_csi_hsync; + u32 pad_csi_pixclk; + u32 pad_i2c1_clk; + u32 pad_i2c1_dat; + u32 pad_cspi1_mosi; + u32 pad_cspi1_miso; + u32 pad_cspi1_ss0; + u32 pad_cspi1_ss1; + u32 pad_cspi1_sclk; + u32 pad_cspi1_rdy; + u32 pad_uart1_rxd; + u32 pad_uart1_txd; + u32 pad_uart1_rts; + u32 pad_uart1_cts; + u32 pad_uart2_rxd; + u32 pad_uart2_txd; + u32 pad_uart2_rts; + u32 pad_uart2_cts; + u32 pad_sd1_cmd; + u32 pad_sd1_clk; + u32 pad_sd1_data0; + u32 pad_sd1_data1; + u32 pad_sd1_data2; + u32 pad_sd1_data3; + u32 pad_kpp_row0; + u32 pad_kpp_row1; + u32 pad_kpp_row2; + u32 pad_kpp_row3; + u32 pad_kpp_col0; + u32 pad_kpp_col1; + u32 pad_kpp_col2; + u32 pad_kpp_col3; + u32 pad_fec_mdc; + u32 pad_fec_mdio; + u32 pad_fec_tdata0; + u32 pad_fec_tdata1; + u32 pad_fec_tx_en; + u32 pad_fec_rdata0; + u32 pad_fec_rdata1; + u32 pad_fec_rx_dv; + u32 pad_fec_tx_clk; + u32 pad_rtck; + u32 pad_de_b; + u32 pad_gpio_a; + u32 pad_gpio_b; + u32 pad_gpio_c; + u32 pad_gpio_d; + u32 pad_gpio_e; + u32 pad_gpio_f; + u32 pad_ext_armclk; + u32 pad_upll_bypclk; + u32 pad_vstby_req; + u32 pad_vstby_ack; + u32 pad_power_fail; + u32 pad_clko; + u32 pad_boot_mode0; + u32 pad_boot_mode1; +}; + +/* + * software pad control + */ +/* Select 3.3 or 1.8 volts */ +#define MX25_PIN_PAD_CTL_DVS_33 (0 << 13) +#define MX25_PIN_PAD_CTL_DVS_18 (1 << 13) +/* Enable hysteresis */ +#define MX25_PIN_PAD_CTL_HYS (1 << 8) +/* Enable pull/keeper */ +#define MX25_PIN_PAD_CTL_PKE (1 << 7) +/* 0 - keeper / 1 - pull */ +#define MX25_PIN_PAD_CTL_PUE (1 << 6) +/* pull up/down strength */ +#define MX25_PIN_PAD_CTL_100K_PD (0 << 4) +#define MX25_PIN_PAD_CTL_47K_PU (1 << 4) +#define MX25_PIN_PAD_CTL_100K_PU (2 << 4) +#define MX25_PIN_PAD_CTL_22K_PU (3 << 4) +/* open drain control */ +#define MX25_PIN_PAD_CTL_OD (1 << 3) +/* drive strength */ +#define MX25_PIN_PAD_CTL_DS_NOM (0 << 1) +#define MX25_PIN_PAD_CTL_DS_HIGH (1 << 1) +#define MX25_PIN_PAD_CTL_DS_MAX (2 << 1) +#define MX25_PIN_PAD_CTL_DS_MAX11 (3 << 1) +/* slew rate */ +#define MX25_PIN_PAD_CTL_SRE_SLOW (0 << 0) +#define MX25_PIN_PAD_CTL_SRE_FAST (1 << 0) +struct iomuxc_pad_ctl { + u32 pad_a13; + u32 pad_a14; + u32 pad_a15; + u32 pad_a17; + u32 pad_a18; + u32 pad_a19; + u32 pad_a20; + u32 pad_a21; + u32 pad_a23; + u32 pad_a24; + u32 pad_a25; + u32 pad_eb0; + u32 pad_eb1; + u32 pad_oe; + u32 pad_cs4; + u32 pad_cs5; + u32 pad_nf_ce0; + u32 pad_ecb; + u32 pad_lba; + u32 pad_rw; + u32 pad_nfrb; + u32 pad_d15; + u32 pad_d14; + u32 pad_d13; + u32 pad_d12; + u32 pad_d11; + u32 pad_d10; + u32 pad_d9; + u32 pad_d8; + u32 pad_d7; + u32 pad_d6; + u32 pad_d5; + u32 pad_d4; + u32 pad_d3; + u32 pad_d2; + u32 pad_d1; + u32 pad_d0; + u32 pad_ld0; + u32 pad_ld1; + u32 pad_ld2; + u32 pad_ld3; + u32 pad_ld4; + u32 pad_ld5; + u32 pad_ld6; + u32 pad_ld7; + u32 pad_ld8; + u32 pad_ld9; + u32 pad_ld10; + u32 pad_ld11; + u32 pad_ld12; + u32 pad_ld13; + u32 pad_ld14; + u32 pad_ld15; + u32 pad_hsync; + u32 pad_vsync; + u32 pad_lsclk; + u32 pad_oe_acd; + u32 pad_contrast; + u32 pad_pwm; + u32 pad_csi_d2; + u32 pad_csi_d3; + u32 pad_csi_d4; + u32 pad_csi_d5; + u32 pad_csi_d6; + u32 pad_csi_d7; + u32 pad_csi_d8; + u32 pad_csi_d9; + u32 pad_csi_mclk; + u32 pad_csi_vsync; + u32 pad_csi_hsync; + u32 pad_csi_pixclk; + u32 pad_i2c1_clk; + u32 pad_i2c1_dat; + u32 pad_cspi1_mosi; + u32 pad_cspi1_miso; + u32 pad_cspi1_ss0; + u32 pad_cspi1_ss1; + u32 pad_cspi1_sclk; + u32 pad_cspi1_rdy; + u32 pad_uart1_rxd; + u32 pad_uart1_txd; + u32 pad_uart1_rts; + u32 pad_uart1_cts; + u32 pad_uart2_rxd; + u32 pad_uart2_txd; + u32 pad_uart2_rts; + u32 pad_uart2_cts; + u32 pad_sd1_cmd; + u32 pad_sd1_clk; + u32 pad_sd1_data0; + u32 pad_sd1_data1; + u32 pad_sd1_data2; + u32 pad_sd1_data3; + u32 pad_kpp_row0; + u32 pad_kpp_row1; + u32 pad_kpp_row2; + u32 pad_kpp_row3; + u32 pad_kpp_col0; + u32 pad_kpp_col1; + u32 pad_kpp_col2; + u32 pad_kpp_col3; + u32 pad_fec_mdc; + u32 pad_fec_mdio; + u32 pad_fec_tdata0; + u32 pad_fec_tdata1; + u32 pad_fec_tx_en; + u32 pad_fec_rdata0; + u32 pad_fec_rdata1; + u32 pad_fec_rx_dv; + u32 pad_fec_tx_clk; + u32 pad_rtck; + u32 pad_tdo; + u32 pad_de_b; + u32 pad_gpio_a; + u32 pad_gpio_b; + u32 pad_gpio_c; + u32 pad_gpio_d; + u32 pad_gpio_e; + u32 pad_gpio_f; + u32 pad_vstby_req; + u32 pad_vstby_ack; + u32 pad_power_fail; + u32 pad_clko; +}; + + +/* + * Pad group drive strength and voltage select + * Same fields as iomuxc_pad_ctl plus ddr type + */ +/* Select DDR type */ +#define MX25_PIN_PAD_CTL_DDR_18 (0 << 11) +#define MX25_PIN_PAD_CTL_DDR_33 (1 << 11) +#define MX25_PIN_PAD_CTL_DDR_MAX (2 << 11) +struct iomuxc_pad_grp_ctl { + u32 grp_dvs_misc; + u32 grp_dse_fec; + u32 grp_dvs_jtag; + u32 grp_dse_nfc; + u32 grp_dse_csi; + u32 grp_dse_weim; + u32 grp_dse_ddr; + u32 grp_dvs_crm; + u32 grp_dse_kpp; + u32 grp_dse_sdhc1; + u32 grp_dse_lcd; + u32 grp_dse_uart; + u32 grp_dvs_nfc; + u32 grp_dvs_csi; + u32 grp_dse_cspi1; + u32 grp_ddrtype; + u32 grp_dvs_sdhc1; + u32 grp_dvs_lcd; +}; + +/* + * Pad input select control + * Select which pad to connect to an input port + * where multiple pads can function as given input + */ +#define MX25_PAD_INPUT_SELECT_DAISY(in) ((in & 0x7) << 0) +struct iomuxc_pad_input_select { + u32 audmux_p4_input_da_amx; + u32 audmux_p4_input_db_amx; + u32 audmux_p4_input_rxclk_amx; + u32 audmux_p4_input_rxfs_amx; + u32 audmux_p4_input_txclk_amx; + u32 audmux_p4_input_txfs_amx; + u32 audmux_p7_input_da_amx; + u32 audmux_p7_input_txfs_amx; + u32 can1_ipp_ind_canrx; + u32 can2_ipp_ind_canrx; + u32 csi_ipp_csi_d_0; + u32 csi_ipp_csi_d_1; + u32 cspi1_ipp_ind_ss3_b; + u32 cspi2_ipp_cspi_clk_in; + u32 cspi2_ipp_ind_dataready_b; + u32 cspi2_ipp_ind_miso; + u32 cspi2_ipp_ind_mosi; + u32 cspi2_ipp_ind_ss0_b; + u32 cspi2_ipp_ind_ss1_b; + u32 cspi3_ipp_cspi_clk_in; + u32 cspi3_ipp_ind_dataready_b; + u32 cspi3_ipp_ind_miso; + u32 cspi3_ipp_ind_mosi; + u32 cspi3_ipp_ind_ss0_b; + u32 cspi3_ipp_ind_ss1_b; + u32 cspi3_ipp_ind_ss2_b; + u32 cspi3_ipp_ind_ss3_b; + u32 esdhc1_ipp_dat4_in; + u32 esdhc1_ipp_dat5_in; + u32 esdhc1_ipp_dat6_in; + u32 esdhc1_ipp_dat7_in; + u32 esdhc2_ipp_card_clk_in; + u32 esdhc2_ipp_cmd_in; + u32 esdhc2_ipp_dat0_in; + u32 esdhc2_ipp_dat1_in; + u32 esdhc2_ipp_dat2_in; + u32 esdhc2_ipp_dat3_in; + u32 esdhc2_ipp_dat4_in; + u32 esdhc2_ipp_dat5_in; + u32 esdhc2_ipp_dat6_in; + u32 esdhc2_ipp_dat7_in; + u32 fec_fec_col; + u32 fec_fec_crs; + u32 fec_fec_rdata_2; + u32 fec_fec_rdata_3; + u32 fec_fec_rx_clk; + u32 fec_fec_rx_er; + u32 i2c2_ipp_scl_in; + u32 i2c2_ipp_sda_in; + u32 i2c3_ipp_scl_in; + u32 i2c3_ipp_sda_in; + u32 kpp_ipp_ind_col_4; + u32 kpp_ipp_ind_col_5; + u32 kpp_ipp_ind_col_6; + u32 kpp_ipp_ind_col_7; + u32 kpp_ipp_ind_row_4; + u32 kpp_ipp_ind_row_5; + u32 kpp_ipp_ind_row_6; + u32 kpp_ipp_ind_row_7; + u32 sim1_pin_sim_rcvd1_in; + u32 sim1_pin_sim_simpd1; + u32 sim1_sim_rcvd1_io; + u32 sim2_pin_sim_rcvd1_in; + u32 sim2_pin_sim_simpd1; + u32 sim2_sim_rcvd1_io; + u32 uart3_ipp_uart_rts_b; + u32 uart3_ipp_uart_rxd_mux; + u32 uart4_ipp_uart_rts_b; + u32 uart4_ipp_uart_rxd_mux; + u32 uart5_ipp_uart_rts_b; + u32 uart5_ipp_uart_rxd_mux; + u32 usb_top_ipp_ind_otg_usb_oc; + u32 usb_top_ipp_ind_uh2_usb_oc; +};